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cobalt / cobalt / 2a8c847d785c1602f60915c8e0112e0aec6a15a5 / . / src / v8 / src / arm / simulator-arm.cc
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// Copyright 2012 the V8 project authors. All rights reserved.
// Use of this source code is governed by a BSD-style license that can be
// found in the LICENSE file.
#include <stdarg.h>
#include <stdlib.h>
#include <cmath>
#if V8_TARGET_ARCH_ARM
#include "src/arm/constants-arm.h"
#include "src/arm/simulator-arm.h"
#include "src/assembler-inl.h"
#include "src/base/bits.h"
#include "src/codegen.h"
#include "src/disasm.h"
#include "src/macro-assembler.h"
#include "src/objects-inl.h"
#include "src/runtime/runtime-utils.h"
#if defined(USE_SIMULATOR)
// Only build the simulator if not compiling for real ARM hardware.
namespace v8 {
namespace internal {
// static
base::LazyInstance<Simulator::GlobalMonitor>::type Simulator::global_monitor_ =
LAZY_INSTANCE_INITIALIZER;
// This macro provides a platform independent use of sscanf. The reason for
// SScanF not being implemented in a platform independent way through
// ::v8::internal::OS in the same way as SNPrintF is that the
// Windows C Run-Time Library does not provide vsscanf.
#define SScanF sscanf // NOLINT
// The ArmDebugger class is used by the simulator while debugging simulated ARM
// code.
class ArmDebugger {
public:
explicit ArmDebugger(Simulator* sim) : sim_(sim) { }
void Stop(Instruction* instr);
void Debug();
private:
static const Instr kBreakpointInstr =
(al | (7*B25) | (1*B24) | kBreakpoint);
static const Instr kNopInstr = (al | (13*B21));
Simulator* sim_;
int32_t GetRegisterValue(int regnum);
double GetRegisterPairDoubleValue(int regnum);
double GetVFPDoubleRegisterValue(int regnum);
bool GetValue(const char* desc, int32_t* value);
bool GetVFPSingleValue(const char* desc, float* value);
bool GetVFPDoubleValue(const char* desc, double* value);
// Set or delete a breakpoint. Returns true if successful.
bool SetBreakpoint(Instruction* breakpc);
bool DeleteBreakpoint(Instruction* breakpc);
// Undo and redo all breakpoints. This is needed to bracket disassembly and
// execution to skip past breakpoints when run from the debugger.
void UndoBreakpoints();
void RedoBreakpoints();
};
void ArmDebugger::Stop(Instruction* instr) {
// Get the stop code.
uint32_t code = instr->SvcValue() & kStopCodeMask;
// Print the stop message and code if it is not the default code.
if (code != kMaxStopCode) {
PrintF("Simulator hit stop %u\n", code);
} else {
PrintF("Simulator hit\n");
}
Debug();
}
int32_t ArmDebugger::GetRegisterValue(int regnum) {
if (regnum == kPCRegister) {
return sim_->get_pc();
} else {
return sim_->get_register(regnum);
}
}
double ArmDebugger::GetRegisterPairDoubleValue(int regnum) {
return sim_->get_double_from_register_pair(regnum);
}
double ArmDebugger::GetVFPDoubleRegisterValue(int regnum) {
return sim_->get_double_from_d_register(regnum).get_scalar();
}
bool ArmDebugger::GetValue(const char* desc, int32_t* value) {
int regnum = Registers::Number(desc);
if (regnum != kNoRegister) {
*value = GetRegisterValue(regnum);
return true;
} else {
if (strncmp(desc, "0x", 2) == 0) {
return SScanF(desc + 2, "%x", reinterpret_cast<uint32_t*>(value)) == 1;
} else {
return SScanF(desc, "%u", reinterpret_cast<uint32_t*>(value)) == 1;
}
}
return false;
}
bool ArmDebugger::GetVFPSingleValue(const char* desc, float* value) {
bool is_double;
int regnum = VFPRegisters::Number(desc, &is_double);
if (regnum != kNoRegister && !is_double) {
*value = sim_->get_float_from_s_register(regnum).get_scalar();
return true;
}
return false;
}
bool ArmDebugger::GetVFPDoubleValue(const char* desc, double* value) {
bool is_double;
int regnum = VFPRegisters::Number(desc, &is_double);
if (regnum != kNoRegister && is_double) {
*value = sim_->get_double_from_d_register(regnum).get_scalar();
return true;
}
return false;
}
bool ArmDebugger::SetBreakpoint(Instruction* breakpc) {
// Check if a breakpoint can be set. If not return without any side-effects.
if (sim_->break_pc_ != nullptr) {
return false;
}
// Set the breakpoint.
sim_->break_pc_ = breakpc;
sim_->break_instr_ = breakpc->InstructionBits();
// Not setting the breakpoint instruction in the code itself. It will be set
// when the debugger shell continues.
return true;
}
bool ArmDebugger::DeleteBreakpoint(Instruction* breakpc) {
if (sim_->break_pc_ != nullptr) {
sim_->break_pc_->SetInstructionBits(sim_->break_instr_);
}
sim_->break_pc_ = nullptr;
sim_->break_instr_ = 0;
return true;
}
void ArmDebugger::UndoBreakpoints() {
if (sim_->break_pc_ != nullptr) {
sim_->break_pc_->SetInstructionBits(sim_->break_instr_);
}
}
void ArmDebugger::RedoBreakpoints() {
if (sim_->break_pc_ != nullptr) {
sim_->break_pc_->SetInstructionBits(kBreakpointInstr);
}
}
void ArmDebugger::Debug() {
intptr_t last_pc = -1;
bool done = false;
#define COMMAND_SIZE 63
#define ARG_SIZE 255
#define STR(a) #a
#define XSTR(a) STR(a)
char cmd[COMMAND_SIZE + 1];
char arg1[ARG_SIZE + 1];
char arg2[ARG_SIZE + 1];
char* argv[3] = { cmd, arg1, arg2 };
// make sure to have a proper terminating character if reaching the limit
cmd[COMMAND_SIZE] = 0;
arg1[ARG_SIZE] = 0;
arg2[ARG_SIZE] = 0;
// Undo all set breakpoints while running in the debugger shell. This will
// make them invisible to all commands.
UndoBreakpoints();
while (!done && !sim_->has_bad_pc()) {
if (last_pc != sim_->get_pc()) {
disasm::NameConverter converter;
disasm::Disassembler dasm(converter);
// use a reasonably large buffer
v8::internal::EmbeddedVector<char, 256> buffer;
dasm.InstructionDecode(buffer,
reinterpret_cast<byte*>(sim_->get_pc()));
PrintF(" 0x%08x %s\n", sim_->get_pc(), buffer.start());
last_pc = sim_->get_pc();
}
char* line = ReadLine("sim> ");
if (line == nullptr) {
break;
} else {
char* last_input = sim_->last_debugger_input();
if (strcmp(line, "\n") == 0 && last_input != nullptr) {
line = last_input;
} else {
// Ownership is transferred to sim_;
sim_->set_last_debugger_input(line);
}
// Use sscanf to parse the individual parts of the command line. At the
// moment no command expects more than two parameters.
int argc = SScanF(line,
"%" XSTR(COMMAND_SIZE) "s "
"%" XSTR(ARG_SIZE) "s "
"%" XSTR(ARG_SIZE) "s",
cmd, arg1, arg2);
if ((strcmp(cmd, "si") == 0) || (strcmp(cmd, "stepi") == 0)) {
sim_->InstructionDecode(reinterpret_cast<Instruction*>(sim_->get_pc()));
} else if ((strcmp(cmd, "c") == 0) || (strcmp(cmd, "cont") == 0)) {
// Execute the one instruction we broke at with breakpoints disabled.
sim_->InstructionDecode(reinterpret_cast<Instruction*>(sim_->get_pc()));
// Leave the debugger shell.
done = true;
} else if ((strcmp(cmd, "p") == 0) || (strcmp(cmd, "print") == 0)) {
if (argc == 2 || (argc == 3 && strcmp(arg2, "fp") == 0)) {
int32_t value;
float svalue;
double dvalue;
if (strcmp(arg1, "all") == 0) {
for (int i = 0; i < kNumRegisters; i++) {
value = GetRegisterValue(i);
PrintF(
"%3s: 0x%08x %10d",
RegisterConfiguration::Default()->GetGeneralRegisterName(i),
value, value);
if ((argc == 3 && strcmp(arg2, "fp") == 0) &&
i < 8 &&
(i % 2) == 0) {
dvalue = GetRegisterPairDoubleValue(i);
PrintF(" (%f)\n", dvalue);
} else {
PrintF("\n");
}
}
for (int i = 0; i < DwVfpRegister::NumRegisters(); i++) {
dvalue = GetVFPDoubleRegisterValue(i);
uint64_t as_words = bit_cast<uint64_t>(dvalue);
PrintF("%3s: %f 0x%08x %08x\n", VFPRegisters::Name(i, true),
dvalue, static_cast<uint32_t>(as_words >> 32),
static_cast<uint32_t>(as_words & 0xFFFFFFFF));
}
} else {
if (GetValue(arg1, &value)) {
PrintF("%s: 0x%08x %d \n", arg1, value, value);
} else if (GetVFPSingleValue(arg1, &svalue)) {
uint32_t as_word = bit_cast<uint32_t>(svalue);
PrintF("%s: %f 0x%08x\n", arg1, svalue, as_word);
} else if (GetVFPDoubleValue(arg1, &dvalue)) {
uint64_t as_words = bit_cast<uint64_t>(dvalue);
PrintF("%s: %f 0x%08x %08x\n", arg1, dvalue,
static_cast<uint32_t>(as_words >> 32),
static_cast<uint32_t>(as_words & 0xFFFFFFFF));
} else {
PrintF("%s unrecognized\n", arg1);
}
}
} else {
PrintF("print <register>\n");
}
} else if ((strcmp(cmd, "po") == 0)
|| (strcmp(cmd, "printobject") == 0)) {
if (argc == 2) {
int32_t value;
OFStream os(stdout);
if (GetValue(arg1, &value)) {
Object* obj = reinterpret_cast<Object*>(value);
os << arg1 << ": \n";
#ifdef DEBUG
obj->Print(os);
os << "\n";
#else
os << Brief(obj) << "\n";
#endif
} else {
os << arg1 << " unrecognized\n";
}
} else {
PrintF("printobject <value>\n");
}
} else if (strcmp(cmd, "stack") == 0 || strcmp(cmd, "mem") == 0) {
int32_t* cur = nullptr;
int32_t* end = nullptr;
int next_arg = 1;
if (strcmp(cmd, "stack") == 0) {
cur = reinterpret_cast<int32_t*>(sim_->get_register(Simulator::sp));
} else { // "mem"
int32_t value;
if (!GetValue(arg1, &value)) {
PrintF("%s unrecognized\n", arg1);
continue;
}
cur = reinterpret_cast<int32_t*>(value);
next_arg++;
}
int32_t words;
if (argc == next_arg) {
words = 10;
} else {
if (!GetValue(argv[next_arg], &words)) {
words = 10;
}
}
end = cur + words;
while (cur < end) {
PrintF(" 0x%08" V8PRIxPTR ": 0x%08x %10d",
reinterpret_cast<intptr_t>(cur), *cur, *cur);
HeapObject* obj = reinterpret_cast<HeapObject*>(*cur);
int value = *cur;
Heap* current_heap = sim_->isolate_->heap();
if (((value & 1) == 0) ||
current_heap->ContainsSlow(obj->address())) {
PrintF(" (");
if ((value & 1) == 0) {
PrintF("smi %d", value / 2);
} else {
obj->ShortPrint();
}
PrintF(")");
}
PrintF("\n");
cur++;
}
} else if (strcmp(cmd, "disasm") == 0 || strcmp(cmd, "di") == 0) {
disasm::NameConverter converter;
disasm::Disassembler dasm(converter);
// use a reasonably large buffer
v8::internal::EmbeddedVector<char, 256> buffer;
byte* prev = nullptr;
byte* cur = nullptr;
byte* end = nullptr;
if (argc == 1) {
cur = reinterpret_cast<byte*>(sim_->get_pc());
end = cur + (10 * Instruction::kInstrSize);
} else if (argc == 2) {
int regnum = Registers::Number(arg1);
if (regnum != kNoRegister || strncmp(arg1, "0x", 2) == 0) {
// The argument is an address or a register name.
int32_t value;
if (GetValue(arg1, &value)) {
cur = reinterpret_cast<byte*>(value);
// Disassemble 10 instructions at <arg1>.
end = cur + (10 * Instruction::kInstrSize);
}
} else {
// The argument is the number of instructions.
int32_t value;
if (GetValue(arg1, &value)) {
cur = reinterpret_cast<byte*>(sim_->get_pc());
// Disassemble <arg1> instructions.
end = cur + (value * Instruction::kInstrSize);
}
}
} else {
int32_t value1;
int32_t value2;
if (GetValue(arg1, &value1) && GetValue(arg2, &value2)) {
cur = reinterpret_cast<byte*>(value1);
end = cur + (value2 * Instruction::kInstrSize);
}
}
while (cur < end) {
prev = cur;
cur += dasm.InstructionDecode(buffer, cur);
PrintF(" 0x%08" V8PRIxPTR " %s\n", reinterpret_cast<intptr_t>(prev),
buffer.start());
}
} else if (strcmp(cmd, "gdb") == 0) {
PrintF("relinquishing control to gdb\n");
v8::base::OS::DebugBreak();
PrintF("regaining control from gdb\n");
} else if (strcmp(cmd, "break") == 0) {
if (argc == 2) {
int32_t value;
if (GetValue(arg1, &value)) {
if (!SetBreakpoint(reinterpret_cast<Instruction*>(value))) {
PrintF("setting breakpoint failed\n");
}
} else {
PrintF("%s unrecognized\n", arg1);
}
} else {
PrintF("break <address>\n");
}
} else if (strcmp(cmd, "del") == 0) {
if (!DeleteBreakpoint(nullptr)) {
PrintF("deleting breakpoint failed\n");
}
} else if (strcmp(cmd, "flags") == 0) {
PrintF("N flag: %d; ", sim_->n_flag_);
PrintF("Z flag: %d; ", sim_->z_flag_);
PrintF("C flag: %d; ", sim_->c_flag_);
PrintF("V flag: %d\n", sim_->v_flag_);
PrintF("INVALID OP flag: %d; ", sim_->inv_op_vfp_flag_);
PrintF("DIV BY ZERO flag: %d; ", sim_->div_zero_vfp_flag_);
PrintF("OVERFLOW flag: %d; ", sim_->overflow_vfp_flag_);
PrintF("UNDERFLOW flag: %d; ", sim_->underflow_vfp_flag_);
PrintF("INEXACT flag: %d;\n", sim_->inexact_vfp_flag_);
} else if (strcmp(cmd, "stop") == 0) {
int32_t value;
intptr_t stop_pc = sim_->get_pc() - Instruction::kInstrSize;
Instruction* stop_instr = reinterpret_cast<Instruction*>(stop_pc);
if ((argc == 2) && (strcmp(arg1, "unstop") == 0)) {
// Remove the current stop.
if (sim_->isStopInstruction(stop_instr)) {
stop_instr->SetInstructionBits(kNopInstr);
} else {
PrintF("Not at debugger stop.\n");
}
} else if (argc == 3) {
// Print information about all/the specified breakpoint(s).
if (strcmp(arg1, "info") == 0) {
if (strcmp(arg2, "all") == 0) {
PrintF("Stop information:\n");
for (uint32_t i = 0; i < sim_->kNumOfWatchedStops; i++) {
sim_->PrintStopInfo(i);
}
} else if (GetValue(arg2, &value)) {
sim_->PrintStopInfo(value);
} else {
PrintF("Unrecognized argument.\n");
}
} else if (strcmp(arg1, "enable") == 0) {
// Enable all/the specified breakpoint(s).
if (strcmp(arg2, "all") == 0) {
for (uint32_t i = 0; i < sim_->kNumOfWatchedStops; i++) {
sim_->EnableStop(i);
}
} else if (GetValue(arg2, &value)) {
sim_->EnableStop(value);
} else {
PrintF("Unrecognized argument.\n");
}
} else if (strcmp(arg1, "disable") == 0) {
// Disable all/the specified breakpoint(s).
if (strcmp(arg2, "all") == 0) {
for (uint32_t i = 0; i < sim_->kNumOfWatchedStops; i++) {
sim_->DisableStop(i);
}
} else if (GetValue(arg2, &value)) {
sim_->DisableStop(value);
} else {
PrintF("Unrecognized argument.\n");
}
}
} else {
PrintF("Wrong usage. Use help command for more information.\n");
}
} else if ((strcmp(cmd, "t") == 0) || strcmp(cmd, "trace") == 0) {
::v8::internal::FLAG_trace_sim = !::v8::internal::FLAG_trace_sim;
PrintF("Trace of executed instructions is %s\n",
::v8::internal::FLAG_trace_sim ? "on" : "off");
} else if ((strcmp(cmd, "h") == 0) || (strcmp(cmd, "help") == 0)) {
PrintF("cont\n");
PrintF(" continue execution (alias 'c')\n");
PrintF("stepi\n");
PrintF(" step one instruction (alias 'si')\n");
PrintF("print <register>\n");
PrintF(" print register content (alias 'p')\n");
PrintF(" use register name 'all' to print all registers\n");
PrintF(" add argument 'fp' to print register pair double values\n");
PrintF("printobject <register>\n");
PrintF(" print an object from a register (alias 'po')\n");
PrintF("flags\n");
PrintF(" print flags\n");
PrintF("stack [<words>]\n");
PrintF(" dump stack content, default dump 10 words)\n");
PrintF("mem <address> [<words>]\n");
PrintF(" dump memory content, default dump 10 words)\n");
PrintF("disasm [<instructions>]\n");
PrintF("disasm [<address/register>]\n");
PrintF("disasm [[<address/register>] <instructions>]\n");
PrintF(" disassemble code, default is 10 instructions\n");
PrintF(" from pc (alias 'di')\n");
PrintF("gdb\n");
PrintF(" enter gdb\n");
PrintF("break <address>\n");
PrintF(" set a break point on the address\n");
PrintF("del\n");
PrintF(" delete the breakpoint\n");
PrintF("trace (alias 't')\n");
PrintF(" toogle the tracing of all executed statements\n");
PrintF("stop feature:\n");
PrintF(" Description:\n");
PrintF(" Stops are debug instructions inserted by\n");
PrintF(" the Assembler::stop() function.\n");
PrintF(" When hitting a stop, the Simulator will\n");
PrintF(" stop and and give control to the ArmDebugger.\n");
PrintF(" The first %d stop codes are watched:\n",
Simulator::kNumOfWatchedStops);
PrintF(" - They can be enabled / disabled: the Simulator\n");
PrintF(" will / won't stop when hitting them.\n");
PrintF(" - The Simulator keeps track of how many times they \n");
PrintF(" are met. (See the info command.) Going over a\n");
PrintF(" disabled stop still increases its counter. \n");
PrintF(" Commands:\n");
PrintF(" stop info all/<code> : print infos about number <code>\n");
PrintF(" or all stop(s).\n");
PrintF(" stop enable/disable all/<code> : enables / disables\n");
PrintF(" all or number <code> stop(s)\n");
PrintF(" stop unstop\n");
PrintF(" ignore the stop instruction at the current location\n");
PrintF(" from now on\n");
} else {
PrintF("Unknown command: %s\n", cmd);
}
}
}
// Add all the breakpoints back to stop execution and enter the debugger
// shell when hit.
RedoBreakpoints();
#undef COMMAND_SIZE
#undef ARG_SIZE
#undef STR
#undef XSTR
}
static bool ICacheMatch(void* one, void* two) {
DCHECK_EQ(reinterpret_cast<intptr_t>(one) & CachePage::kPageMask, 0);
DCHECK_EQ(reinterpret_cast<intptr_t>(two) & CachePage::kPageMask, 0);
return one == two;
}
static uint32_t ICacheHash(void* key) {
return static_cast<uint32_t>(reinterpret_cast<uintptr_t>(key)) >> 2;
}
static bool AllOnOnePage(uintptr_t start, int size) {
intptr_t start_page = (start & ~CachePage::kPageMask);
intptr_t end_page = ((start + size) & ~CachePage::kPageMask);
return start_page == end_page;
}
void Simulator::set_last_debugger_input(char* input) {
DeleteArray(last_debugger_input_);
last_debugger_input_ = input;
}
void Simulator::SetRedirectInstruction(Instruction* instruction) {
instruction->SetInstructionBits(al | (0xF * B24) | kCallRtRedirected);
}
void Simulator::FlushICache(base::CustomMatcherHashMap* i_cache,
void* start_addr, size_t size) {
intptr_t start = reinterpret_cast<intptr_t>(start_addr);
int intra_line = (start & CachePage::kLineMask);
start -= intra_line;
size += intra_line;
size = ((size - 1) | CachePage::kLineMask) + 1;
int offset = (start & CachePage::kPageMask);
while (!AllOnOnePage(start, size - 1)) {
int bytes_to_flush = CachePage::kPageSize - offset;
FlushOnePage(i_cache, start, bytes_to_flush);
start += bytes_to_flush;
size -= bytes_to_flush;
DCHECK_EQ(0, start & CachePage::kPageMask);
offset = 0;
}
if (size != 0) {
FlushOnePage(i_cache, start, size);
}
}
CachePage* Simulator::GetCachePage(base::CustomMatcherHashMap* i_cache,
void* page) {
base::HashMap::Entry* entry = i_cache->LookupOrInsert(page, ICacheHash(page));
if (entry->value == nullptr) {
CachePage* new_page = new CachePage();
entry->value = new_page;
}
return reinterpret_cast<CachePage*>(entry->value);
}
// Flush from start up to and not including start + size.
void Simulator::FlushOnePage(base::CustomMatcherHashMap* i_cache,
intptr_t start, int size) {
DCHECK_LE(size, CachePage::kPageSize);
DCHECK(AllOnOnePage(start, size - 1));
DCHECK_EQ(start & CachePage::kLineMask, 0);
DCHECK_EQ(size & CachePage::kLineMask, 0);
void* page = reinterpret_cast<void*>(start & (~CachePage::kPageMask));
int offset = (start & CachePage::kPageMask);
CachePage* cache_page = GetCachePage(i_cache, page);
char* valid_bytemap = cache_page->ValidityByte(offset);
memset(valid_bytemap, CachePage::LINE_INVALID, size >> CachePage::kLineShift);
}
void Simulator::CheckICache(base::CustomMatcherHashMap* i_cache,
Instruction* instr) {
intptr_t address = reinterpret_cast<intptr_t>(instr);
void* page = reinterpret_cast<void*>(address & (~CachePage::kPageMask));
void* line = reinterpret_cast<void*>(address & (~CachePage::kLineMask));
int offset = (address & CachePage::kPageMask);
CachePage* cache_page = GetCachePage(i_cache, page);
char* cache_valid_byte = cache_page->ValidityByte(offset);
bool cache_hit = (*cache_valid_byte == CachePage::LINE_VALID);
char* cached_line = cache_page->CachedData(offset & ~CachePage::kLineMask);
if (cache_hit) {
// Check that the data in memory matches the contents of the I-cache.
CHECK_EQ(0,
memcmp(reinterpret_cast<void*>(instr),
cache_page->CachedData(offset), Instruction::kInstrSize));
} else {
// Cache miss. Load memory into the cache.
memcpy(cached_line, line, CachePage::kLineLength);
*cache_valid_byte = CachePage::LINE_VALID;
}
}
Simulator::Simulator(Isolate* isolate) : isolate_(isolate) {
i_cache_ = isolate_->simulator_i_cache();
if (i_cache_ == nullptr) {
i_cache_ = new base::CustomMatcherHashMap(&ICacheMatch);
isolate_->set_simulator_i_cache(i_cache_);
}
// Set up simulator support first. Some of this information is needed to
// setup the architecture state.
size_t stack_size = 1 * 1024*1024; // allocate 1MB for stack
stack_ = reinterpret_cast<char*>(malloc(stack_size));
pc_modified_ = false;
icount_ = 0;
break_pc_ = nullptr;
break_instr_ = 0;
// Set up architecture state.
// All registers are initialized to zero to start with.
for (int i = 0; i < num_registers; i++) {
registers_[i] = 0;
}
n_flag_ = false;
z_flag_ = false;
c_flag_ = false;
v_flag_ = false;
// Initializing VFP registers.
// All registers are initialized to zero to start with
// even though s_registers_ & d_registers_ share the same
// physical registers in the target.
for (int i = 0; i < num_d_registers * 2; i++) {
vfp_registers_[i] = 0;
}
n_flag_FPSCR_ = false;
z_flag_FPSCR_ = false;
c_flag_FPSCR_ = false;
v_flag_FPSCR_ = false;
FPSCR_rounding_mode_ = RN;
FPSCR_default_NaN_mode_ = false;
inv_op_vfp_flag_ = false;
div_zero_vfp_flag_ = false;
overflow_vfp_flag_ = false;
underflow_vfp_flag_ = false;
inexact_vfp_flag_ = false;
// The sp is initialized to point to the bottom (high address) of the
// allocated stack area. To be safe in potential stack underflows we leave
// some buffer below.
registers_[sp] = reinterpret_cast<int32_t>(stack_) + stack_size - 64;
// The lr and pc are initialized to a known bad value that will cause an
// access violation if the simulator ever tries to execute it.
registers_[pc] = bad_lr;
registers_[lr] = bad_lr;
last_debugger_input_ = nullptr;
}
Simulator::~Simulator() {
global_monitor_.Pointer()->RemoveProcessor(&global_monitor_processor_);
free(stack_);
}
// Get the active Simulator for the current thread.
Simulator* Simulator::current(Isolate* isolate) {
v8::internal::Isolate::PerIsolateThreadData* isolate_data =
isolate->FindOrAllocatePerThreadDataForThisThread();
DCHECK_NOT_NULL(isolate_data);
Simulator* sim = isolate_data->simulator();
if (sim == nullptr) {
// TODO(146): delete the simulator object when a thread/isolate goes away.
sim = new Simulator(isolate);
isolate_data->set_simulator(sim);
}
return sim;
}
// Sets the register in the architecture state. It will also deal with updating
// Simulator internal state for special registers such as PC.
void Simulator::set_register(int reg, int32_t value) {
DCHECK((reg >= 0) && (reg < num_registers));
if (reg == pc) {
pc_modified_ = true;
}
registers_[reg] = value;
}
// Get the register from the architecture state. This function does handle
// the special case of accessing the PC register.
int32_t Simulator::get_register(int reg) const {
DCHECK((reg >= 0) && (reg < num_registers));
// Stupid code added to avoid bug in GCC.
// See: http://gcc.gnu.org/bugzilla/show_bug.cgi?id=43949
if (reg >= num_registers) return 0;
// End stupid code.
return registers_[reg] + ((reg == pc) ? Instruction::kPCReadOffset : 0);
}
double Simulator::get_double_from_register_pair(int reg) {
DCHECK((reg >= 0) && (reg < num_registers) && ((reg % 2) == 0));
double dm_val = 0.0;
// Read the bits from the unsigned integer register_[] array
// into the double precision floating point value and return it.
char buffer[2 * sizeof(vfp_registers_[0])];
memcpy(buffer, &registers_[reg], 2 * sizeof(registers_[0]));
memcpy(&dm_val, buffer, 2 * sizeof(registers_[0]));
return(dm_val);
}
void Simulator::set_register_pair_from_double(int reg, double* value) {
DCHECK((reg >= 0) && (reg < num_registers) && ((reg % 2) == 0));
memcpy(registers_ + reg, value, sizeof(*value));
}
void Simulator::set_dw_register(int dreg, const int* dbl) {
DCHECK((dreg >= 0) && (dreg < num_d_registers));
registers_[dreg] = dbl[0];
registers_[dreg + 1] = dbl[1];
}
void Simulator::get_d_register(int dreg, uint64_t* value) {
DCHECK((dreg >= 0) && (dreg < DwVfpRegister::NumRegisters()));
memcpy(value, vfp_registers_ + dreg * 2, sizeof(*value));
}
void Simulator::set_d_register(int dreg, const uint64_t* value) {
DCHECK((dreg >= 0) && (dreg < DwVfpRegister::NumRegisters()));
memcpy(vfp_registers_ + dreg * 2, value, sizeof(*value));
}
void Simulator::get_d_register(int dreg, uint32_t* value) {
DCHECK((dreg >= 0) && (dreg < DwVfpRegister::NumRegisters()));
memcpy(value, vfp_registers_ + dreg * 2, sizeof(*value) * 2);
}
void Simulator::set_d_register(int dreg, const uint32_t* value) {
DCHECK((dreg >= 0) && (dreg < DwVfpRegister::NumRegisters()));
memcpy(vfp_registers_ + dreg * 2, value, sizeof(*value) * 2);
}
template <typename T, int SIZE>
void Simulator::get_neon_register(int reg, T (&value)[SIZE / sizeof(T)]) {
DCHECK(SIZE == kSimd128Size || SIZE == kDoubleSize);
DCHECK_LE(0, reg);
DCHECK_GT(SIZE == kSimd128Size ? num_q_registers : num_d_registers, reg);
memcpy(value, vfp_registers_ + reg * (SIZE / 4), SIZE);
}
template <typename T, int SIZE>
void Simulator::set_neon_register(int reg, const T (&value)[SIZE / sizeof(T)]) {
DCHECK(SIZE == kSimd128Size || SIZE == kDoubleSize);
DCHECK_LE(0, reg);
DCHECK_GT(SIZE == kSimd128Size ? num_q_registers : num_d_registers, reg);
memcpy(vfp_registers_ + reg * (SIZE / 4), value, SIZE);
}
// Raw access to the PC register.
void Simulator::set_pc(int32_t value) {
pc_modified_ = true;
registers_[pc] = value;
}
bool Simulator::has_bad_pc() const {
return ((registers_[pc] == bad_lr) || (registers_[pc] == end_sim_pc));
}
// Raw access to the PC register without the special adjustment when reading.
int32_t Simulator::get_pc() const {
return registers_[pc];
}
// Getting from and setting into VFP registers.
void Simulator::set_s_register(int sreg, unsigned int value) {
DCHECK((sreg >= 0) && (sreg < num_s_registers));
vfp_registers_[sreg] = value;
}
unsigned int Simulator::get_s_register(int sreg) const {
DCHECK((sreg >= 0) && (sreg < num_s_registers));
return vfp_registers_[sreg];
}
template<class InputType, int register_size>
void Simulator::SetVFPRegister(int reg_index, const InputType& value) {
unsigned bytes = register_size * sizeof(vfp_registers_[0]);
DCHECK_EQ(sizeof(InputType), bytes);
DCHECK_GE(reg_index, 0);
if (register_size == 1) DCHECK(reg_index < num_s_registers);
if (register_size == 2) DCHECK(reg_index < DwVfpRegister::NumRegisters());
memcpy(&vfp_registers_[reg_index * register_size], &value, bytes);
}
template<class ReturnType, int register_size>
ReturnType Simulator::GetFromVFPRegister(int reg_index) {
unsigned bytes = register_size * sizeof(vfp_registers_[0]);
DCHECK_EQ(sizeof(ReturnType), bytes);
DCHECK_GE(reg_index, 0);
if (register_size == 1) DCHECK(reg_index < num_s_registers);
if (register_size == 2) DCHECK(reg_index < DwVfpRegister::NumRegisters());
ReturnType value;
memcpy(&value, &vfp_registers_[register_size * reg_index], bytes);
return value;
}
void Simulator::SetSpecialRegister(SRegisterFieldMask reg_and_mask,
uint32_t value) {
// Only CPSR_f is implemented. Of that, only N, Z, C and V are implemented.
if ((reg_and_mask == CPSR_f) && ((value & ~kSpecialCondition) == 0)) {
n_flag_ = ((value & (1 << 31)) != 0);
z_flag_ = ((value & (1 << 30)) != 0);
c_flag_ = ((value & (1 << 29)) != 0);
v_flag_ = ((value & (1 << 28)) != 0);
} else {
UNIMPLEMENTED();
}
}
uint32_t Simulator::GetFromSpecialRegister(SRegister reg) {
uint32_t result = 0;
// Only CPSR_f is implemented.
if (reg == CPSR) {
if (n_flag_) result |= (1 << 31);
if (z_flag_) result |= (1 << 30);
if (c_flag_) result |= (1 << 29);
if (v_flag_) result |= (1 << 28);
} else {
UNIMPLEMENTED();
}
return result;
}
// Runtime FP routines take:
// - two double arguments
// - one double argument and zero or one integer arguments.
// All are consructed here from r0-r3 or d0, d1 and r0.
void Simulator::GetFpArgs(double* x, double* y, int32_t* z) {
if (use_eabi_hardfloat()) {
*x = get_double_from_d_register(0).get_scalar();
*y = get_double_from_d_register(1).get_scalar();
*z = get_register(0);
} else {
// Registers 0 and 1 -> x.
*x = get_double_from_register_pair(0);
// Register 2 and 3 -> y.
*y = get_double_from_register_pair(2);
// Register 2 -> z
*z = get_register(2);
}
}
// The return value is either in r0/r1 or d0.
void Simulator::SetFpResult(const double& result) {
if (use_eabi_hardfloat()) {
char buffer[2 * sizeof(vfp_registers_[0])];
memcpy(buffer, &result, sizeof(buffer));
// Copy result to d0.
memcpy(vfp_registers_, buffer, sizeof(buffer));
} else {
char buffer[2 * sizeof(registers_[0])];
memcpy(buffer, &result, sizeof(buffer));
// Copy result to r0 and r1.
memcpy(registers_, buffer, sizeof(buffer));
}
}
void Simulator::TrashCallerSaveRegisters() {
// We don't trash the registers with the return value.
registers_[2] = 0x50BAD4U;
registers_[3] = 0x50BAD4U;
registers_[12] = 0x50BAD4U;
}
int Simulator::ReadW(int32_t addr, Instruction* instr) {
// All supported ARM targets allow unaligned accesses, so we don't need to
// check the alignment here.
base::LockGuard<base::Mutex> lock_guard(&global_monitor_.Pointer()->mutex);
local_monitor_.NotifyLoad(addr);
intptr_t* ptr = reinterpret_cast<intptr_t*>(addr);
return *ptr;
}
int Simulator::ReadExW(int32_t addr, Instruction* instr) {
base::LockGuard<base::Mutex> lock_guard(&global_monitor_.Pointer()->mutex);
local_monitor_.NotifyLoadExcl(addr, TransactionSize::Word);
global_monitor_.Pointer()->NotifyLoadExcl_Locked(addr,
&global_monitor_processor_);
intptr_t* ptr = reinterpret_cast<intptr_t*>(addr);
return *ptr;
}
void Simulator::WriteW(int32_t addr, int value, Instruction* instr) {
// All supported ARM targets allow unaligned accesses, so we don't need to
// check the alignment here.
base::LockGuard<base::Mutex> lock_guard(&global_monitor_.Pointer()->mutex);
local_monitor_.NotifyStore(addr);
global_monitor_.Pointer()->NotifyStore_Locked(addr,
&global_monitor_processor_);
intptr_t* ptr = reinterpret_cast<intptr_t*>(addr);
*ptr = value;
}
int Simulator::WriteExW(int32_t addr, int value, Instruction* instr) {
base::LockGuard<base::Mutex> lock_guard(&global_monitor_.Pointer()->mutex);
if (local_monitor_.NotifyStoreExcl(addr, TransactionSize::Word) &&
global_monitor_.Pointer()->NotifyStoreExcl_Locked(
addr, &global_monitor_processor_)) {
intptr_t* ptr = reinterpret_cast<intptr_t*>(addr);
*ptr = value;
return 0;
} else {
return 1;
}
}
uint16_t Simulator::ReadHU(int32_t addr, Instruction* instr) {
// All supported ARM targets allow unaligned accesses, so we don't need to
// check the alignment here.
base::LockGuard<base::Mutex> lock_guard(&global_monitor_.Pointer()->mutex);
local_monitor_.NotifyLoad(addr);
uint16_t* ptr = reinterpret_cast<uint16_t*>(addr);
return *ptr;
}
int16_t Simulator::ReadH(int32_t addr, Instruction* instr) {
// All supported ARM targets allow unaligned accesses, so we don't need to
// check the alignment here.
base::LockGuard<base::Mutex> lock_guard(&global_monitor_.Pointer()->mutex);
local_monitor_.NotifyLoad(addr);
int16_t* ptr = reinterpret_cast<int16_t*>(addr);
return *ptr;
}
uint16_t Simulator::ReadExHU(int32_t addr, Instruction* instr) {
base::LockGuard<base::Mutex> lock_guard(&global_monitor_.Pointer()->mutex);
local_monitor_.NotifyLoadExcl(addr, TransactionSize::HalfWord);
global_monitor_.Pointer()->NotifyLoadExcl_Locked(addr,
&global_monitor_processor_);
uint16_t* ptr = reinterpret_cast<uint16_t*>(addr);
return *ptr;
}
void Simulator::WriteH(int32_t addr, uint16_t value, Instruction* instr) {
// All supported ARM targets allow unaligned accesses, so we don't need to
// check the alignment here.
base::LockGuard<base::Mutex> lock_guard(&global_monitor_.Pointer()->mutex);
local_monitor_.NotifyStore(addr);
global_monitor_.Pointer()->NotifyStore_Locked(addr,
&global_monitor_processor_);
uint16_t* ptr = reinterpret_cast<uint16_t*>(addr);
*ptr = value;
}
void Simulator::WriteH(int32_t addr, int16_t value, Instruction* instr) {
// All supported ARM targets allow unaligned accesses, so we don't need to
// check the alignment here.
base::LockGuard<base::Mutex> lock_guard(&global_monitor_.Pointer()->mutex);
local_monitor_.NotifyStore(addr);
global_monitor_.Pointer()->NotifyStore_Locked(addr,
&global_monitor_processor_);
int16_t* ptr = reinterpret_cast<int16_t*>(addr);
*ptr = value;
}
int Simulator::WriteExH(int32_t addr, uint16_t value, Instruction* instr) {
base::LockGuard<base::Mutex> lock_guard(&global_monitor_.Pointer()->mutex);
if (local_monitor_.NotifyStoreExcl(addr, TransactionSize::HalfWord) &&
global_monitor_.Pointer()->NotifyStoreExcl_Locked(
addr, &global_monitor_processor_)) {
uint16_t* ptr = reinterpret_cast<uint16_t*>(addr);
*ptr = value;
return 0;
} else {
return 1;
}
}
uint8_t Simulator::ReadBU(int32_t addr) {
base::LockGuard<base::Mutex> lock_guard(&global_monitor_.Pointer()->mutex);
local_monitor_.NotifyLoad(addr);
uint8_t* ptr = reinterpret_cast<uint8_t*>(addr);
return *ptr;
}
int8_t Simulator::ReadB(int32_t addr) {
base::LockGuard<base::Mutex> lock_guard(&global_monitor_.Pointer()->mutex);
local_monitor_.NotifyLoad(addr);
int8_t* ptr = reinterpret_cast<int8_t*>(addr);
return *ptr;
}
uint8_t Simulator::ReadExBU(int32_t addr) {
base::LockGuard<base::Mutex> lock_guard(&global_monitor_.Pointer()->mutex);
local_monitor_.NotifyLoadExcl(addr, TransactionSize::Byte);
global_monitor_.Pointer()->NotifyLoadExcl_Locked(addr,
&global_monitor_processor_);
uint8_t* ptr = reinterpret_cast<uint8_t*>(addr);
return *ptr;
}
void Simulator::WriteB(int32_t addr, uint8_t value) {
base::LockGuard<base::Mutex> lock_guard(&global_monitor_.Pointer()->mutex);
local_monitor_.NotifyStore(addr);
global_monitor_.Pointer()->NotifyStore_Locked(addr,
&global_monitor_processor_);
uint8_t* ptr = reinterpret_cast<uint8_t*>(addr);
*ptr = value;
}
void Simulator::WriteB(int32_t addr, int8_t value) {
base::LockGuard<base::Mutex> lock_guard(&global_monitor_.Pointer()->mutex);
local_monitor_.NotifyStore(addr);
global_monitor_.Pointer()->NotifyStore_Locked(addr,
&global_monitor_processor_);
int8_t* ptr = reinterpret_cast<int8_t*>(addr);
*ptr = value;
}
int Simulator::WriteExB(int32_t addr, uint8_t value) {
base::LockGuard<base::Mutex> lock_guard(&global_monitor_.Pointer()->mutex);
if (local_monitor_.NotifyStoreExcl(addr, TransactionSize::Byte) &&
global_monitor_.Pointer()->NotifyStoreExcl_Locked(
addr, &global_monitor_processor_)) {
uint8_t* ptr = reinterpret_cast<uint8_t*>(addr);
*ptr = value;
return 0;
} else {
return 1;
}
}
int32_t* Simulator::ReadDW(int32_t addr) {
// All supported ARM targets allow unaligned accesses, so we don't need to
// check the alignment here.
base::LockGuard<base::Mutex> lock_guard(&global_monitor_.Pointer()->mutex);
local_monitor_.NotifyLoad(addr);
int32_t* ptr = reinterpret_cast<int32_t*>(addr);
return ptr;
}
void Simulator::WriteDW(int32_t addr, int32_t value1, int32_t value2) {
// All supported ARM targets allow unaligned accesses, so we don't need to
// check the alignment here.
base::LockGuard<base::Mutex> lock_guard(&global_monitor_.Pointer()->mutex);
local_monitor_.NotifyStore(addr);
global_monitor_.Pointer()->NotifyStore_Locked(addr,
&global_monitor_processor_);
int32_t* ptr = reinterpret_cast<int32_t*>(addr);
*ptr++ = value1;
*ptr = value2;
}
// Returns the limit of the stack area to enable checking for stack overflows.
uintptr_t Simulator::StackLimit(uintptr_t c_limit) const {
// The simulator uses a separate JS stack. If we have exhausted the C stack,
// we also drop down the JS limit to reflect the exhaustion on the JS stack.
if (GetCurrentStackPosition() < c_limit) {
return reinterpret_cast<uintptr_t>(get_sp());
}
// Otherwise the limit is the JS stack. Leave a safety margin of 1024 bytes
// to prevent overrunning the stack when pushing values.
return reinterpret_cast<uintptr_t>(stack_) + 1024;
}
// Unsupported instructions use Format to print an error and stop execution.
void Simulator::Format(Instruction* instr, const char* format) {
PrintF("Simulator found unsupported instruction:\n 0x%08" V8PRIxPTR ": %s\n",
reinterpret_cast<intptr_t>(instr), format);
UNIMPLEMENTED();
}
// Checks if the current instruction should be executed based on its
// condition bits.
bool Simulator::ConditionallyExecute(Instruction* instr) {
switch (instr->ConditionField()) {
case eq: return z_flag_;
case ne: return !z_flag_;
case cs: return c_flag_;
case cc: return !c_flag_;
case mi: return n_flag_;
case pl: return !n_flag_;
case vs: return v_flag_;
case vc: return !v_flag_;
case hi: return c_flag_ && !z_flag_;
case ls: return !c_flag_ || z_flag_;
case ge: return n_flag_ == v_flag_;
case lt: return n_flag_ != v_flag_;
case gt: return !z_flag_ && (n_flag_ == v_flag_);
case le: return z_flag_ || (n_flag_ != v_flag_);
case al: return true;
default: UNREACHABLE();
}
return false;
}
// Calculate and set the Negative and Zero flags.
void Simulator::SetNZFlags(int32_t val) {
n_flag_ = (val < 0);
z_flag_ = (val == 0);
}
// Set the Carry flag.
void Simulator::SetCFlag(bool val) {
c_flag_ = val;
}
// Set the oVerflow flag.
void Simulator::SetVFlag(bool val) {
v_flag_ = val;
}
// Calculate C flag value for additions.
bool Simulator::CarryFrom(int32_t left, int32_t right, int32_t carry) {
uint32_t uleft = static_cast<uint32_t>(left);
uint32_t uright = static_cast<uint32_t>(right);
uint32_t urest = 0xFFFFFFFFU - uleft;
return (uright > urest) ||
(carry && (((uright + 1) > urest) || (uright > (urest - 1))));
}
// Calculate C flag value for subtractions.
bool Simulator::BorrowFrom(int32_t left, int32_t right, int32_t carry) {
uint32_t uleft = static_cast<uint32_t>(left);
uint32_t uright = static_cast<uint32_t>(right);
return (uright > uleft) ||
(!carry && (((uright + 1) > uleft) || (uright > (uleft - 1))));
}
// Calculate V flag value for additions and subtractions.
bool Simulator::OverflowFrom(int32_t alu_out,
int32_t left, int32_t right, bool addition) {
bool overflow;
if (addition) {
// operands have the same sign
overflow = ((left >= 0 && right >= 0) || (left < 0 && right < 0))
// and operands and result have different sign
&& ((left < 0 && alu_out >= 0) || (left >= 0 && alu_out < 0));
} else {
// operands have different signs
overflow = ((left < 0 && right >= 0) || (left >= 0 && right < 0))
// and first operand and result have different signs
&& ((left < 0 && alu_out >= 0) || (left >= 0 && alu_out < 0));
}
return overflow;
}
// Support for VFP comparisons.
void Simulator::Compute_FPSCR_Flags(float val1, float val2) {
if (std::isnan(val1) || std::isnan(val2)) {
n_flag_FPSCR_ = false;
z_flag_FPSCR_ = false;
c_flag_FPSCR_ = true;
v_flag_FPSCR_ = true;
// All non-NaN cases.
} else if (val1 == val2) {
n_flag_FPSCR_ = false;
z_flag_FPSCR_ = true;
c_flag_FPSCR_ = true;
v_flag_FPSCR_ = false;
} else if (val1 < val2) {
n_flag_FPSCR_ = true;
z_flag_FPSCR_ = false;
c_flag_FPSCR_ = false;
v_flag_FPSCR_ = false;
} else {
// Case when (val1 > val2).
n_flag_FPSCR_ = false;
z_flag_FPSCR_ = false;
c_flag_FPSCR_ = true;
v_flag_FPSCR_ = false;
}
}
void Simulator::Compute_FPSCR_Flags(double val1, double val2) {
if (std::isnan(val1) || std::isnan(val2)) {
n_flag_FPSCR_ = false;
z_flag_FPSCR_ = false;
c_flag_FPSCR_ = true;
v_flag_FPSCR_ = true;
// All non-NaN cases.
} else if (val1 == val2) {
n_flag_FPSCR_ = false;
z_flag_FPSCR_ = true;
c_flag_FPSCR_ = true;
v_flag_FPSCR_ = false;
} else if (val1 < val2) {
n_flag_FPSCR_ = true;
z_flag_FPSCR_ = false;
c_flag_FPSCR_ = false;
v_flag_FPSCR_ = false;
} else {
// Case when (val1 > val2).
n_flag_FPSCR_ = false;
z_flag_FPSCR_ = false;
c_flag_FPSCR_ = true;
v_flag_FPSCR_ = false;
}
}
void Simulator::Copy_FPSCR_to_APSR() {
n_flag_ = n_flag_FPSCR_;
z_flag_ = z_flag_FPSCR_;
c_flag_ = c_flag_FPSCR_;
v_flag_ = v_flag_FPSCR_;
}
// Addressing Mode 1 - Data-processing operands:
// Get the value based on the shifter_operand with register.
int32_t Simulator::GetShiftRm(Instruction* instr, bool* carry_out) {
ShiftOp shift = instr->ShiftField();
int shift_amount = instr->ShiftAmountValue();
int32_t result = get_register(instr->RmValue());
if (instr->Bit(4) == 0) {
// by immediate
if ((shift == ROR) && (shift_amount == 0)) {
UNIMPLEMENTED();
return result;
} else if (((shift == LSR) || (shift == ASR)) && (shift_amount == 0)) {
shift_amount = 32;
}
switch (shift) {
case ASR: {
if (shift_amount == 0) {
if (result < 0) {
result = 0xFFFFFFFF;
*carry_out = true;
} else {
result = 0;
*carry_out = false;
}
} else {
result >>= (shift_amount - 1);
*carry_out = (result & 1) == 1;
result >>= 1;
}
break;
}
case LSL: {
if (shift_amount == 0) {
*carry_out = c_flag_;
} else {
result <<= (shift_amount - 1);
*carry_out = (result < 0);
result <<= 1;
}
break;
}
case LSR: {
if (shift_amount == 0) {
result = 0;
*carry_out = c_flag_;
} else {
uint32_t uresult = static_cast<uint32_t>(result);
uresult >>= (shift_amount - 1);
*carry_out = (uresult & 1) == 1;
uresult >>= 1;
result = static_cast<int32_t>(uresult);
}
break;
}
case ROR: {
if (shift_amount == 0) {
*carry_out = c_flag_;
} else {
uint32_t left = static_cast<uint32_t>(result) >> shift_amount;
uint32_t right = static_cast<uint32_t>(result) << (32 - shift_amount);
result = right | left;
*carry_out = (static_cast<uint32_t>(result) >> 31) != 0;
}
break;
}
default: {
UNREACHABLE();
break;
}
}
} else {
// by register
int rs = instr->RsValue();
shift_amount = get_register(rs) & 0xFF;
switch (shift) {
case ASR: {
if (shift_amount == 0) {
*carry_out = c_flag_;
} else if (shift_amount < 32) {
result >>= (shift_amount - 1);
*carry_out = (result & 1) == 1;
result >>= 1;
} else {
DCHECK_GE(shift_amount, 32);
if (result < 0) {
*carry_out = true;
result = 0xFFFFFFFF;
} else {
*carry_out = false;
result = 0;
}
}
break;
}
case LSL: {
if (shift_amount == 0) {
*carry_out = c_flag_;
} else if (shift_amount < 32) {
result <<= (shift_amount - 1);
*carry_out = (result < 0);
result <<= 1;
} else if (shift_amount == 32) {
*carry_out = (result & 1) == 1;
result = 0;
} else {
DCHECK_GT(shift_amount, 32);
*carry_out = false;
result = 0;
}
break;
}
case LSR: {
if (shift_amount == 0) {
*carry_out = c_flag_;
} else if (shift_amount < 32) {
uint32_t uresult = static_cast<uint32_t>(result);
uresult >>= (shift_amount - 1);
*carry_out = (uresult & 1) == 1;
uresult >>= 1;
result = static_cast<int32_t>(uresult);
} else if (shift_amount == 32) {
*carry_out = (result < 0);
result = 0;
} else {
*carry_out = false;
result = 0;
}
break;
}
case ROR: {
if (shift_amount == 0) {
*carry_out = c_flag_;
} else {
uint32_t left = static_cast<uint32_t>(result) >> shift_amount;
uint32_t right = static_cast<uint32_t>(result) << (32 - shift_amount);
result = right | left;
*carry_out = (static_cast<uint32_t>(result) >> 31) != 0;
}
break;
}
default: {
UNREACHABLE();
break;
}
}
}
return result;
}
// Addressing Mode 1 - Data-processing operands:
// Get the value based on the shifter_operand with immediate.
int32_t Simulator::GetImm(Instruction* instr, bool* carry_out) {
int rotate = instr->RotateValue() * 2;
int immed8 = instr->Immed8Value();
int imm = base::bits::RotateRight32(immed8, rotate);
*carry_out = (rotate == 0) ? c_flag_ : (imm < 0);
return imm;
}
static int count_bits(int bit_vector) {
int count = 0;
while (bit_vector != 0) {
if ((bit_vector & 1) != 0) {
count++;
}
bit_vector >>= 1;
}
return count;
}
int32_t Simulator::ProcessPU(Instruction* instr,
int num_regs,
int reg_size,
intptr_t* start_address,
intptr_t* end_address) {
int rn = instr->RnValue();
int32_t rn_val = get_register(rn);
switch (instr->PUField()) {
case da_x: {
UNIMPLEMENTED();
break;
}
case ia_x: {
*start_address = rn_val;
*end_address = rn_val + (num_regs * reg_size) - reg_size;
rn_val = rn_val + (num_regs * reg_size);
break;
}
case db_x: {
*start_address = rn_val - (num_regs * reg_size);
*end_address = rn_val - reg_size;
rn_val = *start_address;
break;
}
case ib_x: {
*start_address = rn_val + reg_size;
*end_address = rn_val + (num_regs * reg_size);
rn_val = *end_address;
break;
}
default: {
UNREACHABLE();
break;
}
}
return rn_val;
}
// Addressing Mode 4 - Load and Store Multiple
void Simulator::HandleRList(Instruction* instr, bool load) {
int rlist = instr->RlistValue();
int num_regs = count_bits(rlist);
intptr_t start_address = 0;
intptr_t end_address = 0;
int32_t rn_val =
ProcessPU(instr, num_regs, kPointerSize, &start_address, &end_address);
intptr_t* address = reinterpret_cast<intptr_t*>(start_address);
// Catch null pointers a little earlier.
DCHECK(start_address > 8191 || start_address < 0);
int reg = 0;
while (rlist != 0) {
if ((rlist & 1) != 0) {
if (load) {
set_register(reg, *address);
} else {
*address = get_register(reg);
}
address += 1;
}
reg++;
rlist >>= 1;
}
DCHECK(end_address == ((intptr_t)address) - 4);
if (instr->HasW()) {
set_register(instr->RnValue(), rn_val);
}
}
// Addressing Mode 6 - Load and Store Multiple Coprocessor registers.
void Simulator::HandleVList(Instruction* instr) {
VFPRegPrecision precision =
(instr->SzValue() == 0) ? kSinglePrecision : kDoublePrecision;
int operand_size = (precision == kSinglePrecision) ? 4 : 8;
bool load = (instr->VLValue() == 0x1);
int vd;
int num_regs;
vd = instr->VFPDRegValue(precision);
if (precision == kSinglePrecision) {
num_regs = instr->Immed8Value();
} else {
num_regs = instr->Immed8Value() / 2;
}
intptr_t start_address = 0;
intptr_t end_address = 0;
int32_t rn_val =
ProcessPU(instr, num_regs, operand_size, &start_address, &end_address);
intptr_t* address = reinterpret_cast<intptr_t*>(start_address);
for (int reg = vd; reg < vd + num_regs; reg++) {
if (precision == kSinglePrecision) {
if (load) {
set_s_register_from_sinteger(
reg, ReadW(reinterpret_cast<int32_t>(address), instr));
} else {
WriteW(reinterpret_cast<int32_t>(address),
get_sinteger_from_s_register(reg), instr);
}
address += 1;
} else {
if (load) {
int32_t data[] = {
ReadW(reinterpret_cast<int32_t>(address), instr),
ReadW(reinterpret_cast<int32_t>(address + 1), instr)
};
set_d_register(reg, reinterpret_cast<uint32_t*>(data));
} else {
uint32_t data[2];
get_d_register(reg, data);
WriteW(reinterpret_cast<int32_t>(address), data[0], instr);
WriteW(reinterpret_cast<int32_t>(address + 1), data[1], instr);
}
address += 2;
}
}
DCHECK(reinterpret_cast<intptr_t>(address) - operand_size == end_address);
if (instr->HasW()) {
set_register(instr->RnValue(), rn_val);
}
}
// Calls into the V8 runtime are based on this very simple interface.
// Note: To be able to return two values from some calls the code in runtime.cc
// uses the ObjectPair which is essentially two 32-bit values stuffed into a
// 64-bit value. With the code below we assume that all runtime calls return
// 64 bits of result. If they don't, the r1 result register contains a bogus
// value, which is fine because it is caller-saved.
typedef int64_t (*SimulatorRuntimeCall)(int32_t arg0, int32_t arg1,
int32_t arg2, int32_t arg3,
int32_t arg4, int32_t arg5,
int32_t arg6, int32_t arg7,
int32_t arg8);
// These prototypes handle the four types of FP calls.
typedef int64_t (*SimulatorRuntimeCompareCall)(double darg0, double darg1);
typedef double (*SimulatorRuntimeFPFPCall)(double darg0, double darg1);
typedef double (*SimulatorRuntimeFPCall)(double darg0);
typedef double (*SimulatorRuntimeFPIntCall)(double darg0, int32_t arg0);
// This signature supports direct call in to API function native callback
// (refer to InvocationCallback in v8.h).
typedef void (*SimulatorRuntimeDirectApiCall)(int32_t arg0);
typedef void (*SimulatorRuntimeProfilingApiCall)(int32_t arg0, void* arg1);
// This signature supports direct call to accessor getter callback.
typedef void (*SimulatorRuntimeDirectGetterCall)(int32_t arg0, int32_t arg1);
typedef void (*SimulatorRuntimeProfilingGetterCall)(
int32_t arg0, int32_t arg1, void* arg2);
// Software interrupt instructions are used by the simulator to call into the
// C-based V8 runtime.
void Simulator::SoftwareInterrupt(Instruction* instr) {
int svc = instr->SvcValue();
switch (svc) {
case kCallRtRedirected: {
// Check if stack is aligned. Error if not aligned is reported below to
// include information on the function called.
bool stack_aligned =
(get_register(sp)
& (::v8::internal::FLAG_sim_stack_alignment - 1)) == 0;
Redirection* redirection = Redirection::FromInstruction(instr);
int32_t arg0 = get_register(r0);
int32_t arg1 = get_register(r1);
int32_t arg2 = get_register(r2);
int32_t arg3 = get_register(r3);
int32_t* stack_pointer = reinterpret_cast<int32_t*>(get_register(sp));
int32_t arg4 = stack_pointer[0];
int32_t arg5 = stack_pointer[1];
int32_t arg6 = stack_pointer[2];
int32_t arg7 = stack_pointer[3];
int32_t arg8 = stack_pointer[4];
STATIC_ASSERT(kMaxCParameters == 9);
bool fp_call =
(redirection->type() == ExternalReference::BUILTIN_FP_FP_CALL) ||
(redirection->type() == ExternalReference::BUILTIN_COMPARE_CALL) ||
(redirection->type() == ExternalReference::BUILTIN_FP_CALL) ||
(redirection->type() == ExternalReference::BUILTIN_FP_INT_CALL);
// This is dodgy but it works because the C entry stubs are never moved.
// See comment in codegen-arm.cc and bug 1242173.
int32_t saved_lr = get_register(lr);
intptr_t external =
reinterpret_cast<intptr_t>(redirection->external_function());
if (fp_call) {
double dval0, dval1; // one or two double parameters
int32_t ival; // zero or one integer parameters
int64_t iresult = 0; // integer return value
double dresult = 0; // double return value
GetFpArgs(&dval0, &dval1, &ival);
if (::v8::internal::FLAG_trace_sim || !stack_aligned) {
SimulatorRuntimeCall generic_target =
reinterpret_cast<SimulatorRuntimeCall>(external);
switch (redirection->type()) {
case ExternalReference::BUILTIN_FP_FP_CALL:
case ExternalReference::BUILTIN_COMPARE_CALL:
PrintF("Call to host function at %p with args %f, %f",
static_cast<void*>(FUNCTION_ADDR(generic_target)), dval0,
dval1);
break;
case ExternalReference::BUILTIN_FP_CALL:
PrintF("Call to host function at %p with arg %f",
static_cast<void*>(FUNCTION_ADDR(generic_target)), dval0);
break;
case ExternalReference::BUILTIN_FP_INT_CALL:
PrintF("Call to host function at %p with args %f, %d",
static_cast<void*>(FUNCTION_ADDR(generic_target)), dval0,
ival);
break;
default:
UNREACHABLE();
break;
}
if (!stack_aligned) {
PrintF(" with unaligned stack %08x\n", get_register(sp));
}
PrintF("\n");
}
CHECK(stack_aligned);
switch (redirection->type()) {
case ExternalReference::BUILTIN_COMPARE_CALL: {
SimulatorRuntimeCompareCall target =
reinterpret_cast<SimulatorRuntimeCompareCall>(external);
iresult = target(dval0, dval1);
set_register(r0, static_cast<int32_t>(iresult));
set_register(r1, static_cast<int32_t>(iresult >> 32));
break;
}
case ExternalReference::BUILTIN_FP_FP_CALL: {
SimulatorRuntimeFPFPCall target =
reinterpret_cast<SimulatorRuntimeFPFPCall>(external);
dresult = target(dval0, dval1);
SetFpResult(dresult);
break;
}
case ExternalReference::BUILTIN_FP_CALL: {
SimulatorRuntimeFPCall target =
reinterpret_cast<SimulatorRuntimeFPCall>(external);
dresult = target(dval0);
SetFpResult(dresult);
break;
}
case ExternalReference::BUILTIN_FP_INT_CALL: {
SimulatorRuntimeFPIntCall target =
reinterpret_cast<SimulatorRuntimeFPIntCall>(external);
dresult = target(dval0, ival);
SetFpResult(dresult);
break;
}
default:
UNREACHABLE();
break;
}
if (::v8::internal::FLAG_trace_sim || !stack_aligned) {
switch (redirection->type()) {
case ExternalReference::BUILTIN_COMPARE_CALL:
PrintF("Returned %08x\n", static_cast<int32_t>(iresult));
break;
case ExternalReference::BUILTIN_FP_FP_CALL:
case ExternalReference::BUILTIN_FP_CALL:
case ExternalReference::BUILTIN_FP_INT_CALL:
PrintF("Returned %f\n", dresult);
break;
default:
UNREACHABLE();
break;
}
}
} else if (redirection->type() == ExternalReference::DIRECT_API_CALL) {
if (::v8::internal::FLAG_trace_sim || !stack_aligned) {
PrintF("Call to host function at %p args %08x",
reinterpret_cast<void*>(external), arg0);
if (!stack_aligned) {
PrintF(" with unaligned stack %08x\n", get_register(sp));
}
PrintF("\n");
}
CHECK(stack_aligned);
SimulatorRuntimeDirectApiCall target =
reinterpret_cast<SimulatorRuntimeDirectApiCall>(external);
target(arg0);
} else if (
redirection->type() == ExternalReference::PROFILING_API_CALL) {
if (::v8::internal::FLAG_trace_sim || !stack_aligned) {
PrintF("Call to host function at %p args %08x %08x",
reinterpret_cast<void*>(external), arg0, arg1);
if (!stack_aligned) {
PrintF(" with unaligned stack %08x\n", get_register(sp));
}
PrintF("\n");
}
CHECK(stack_aligned);
SimulatorRuntimeProfilingApiCall target =
reinterpret_cast<SimulatorRuntimeProfilingApiCall>(external);
target(arg0, Redirection::ReverseRedirection(arg1));
} else if (
redirection->type() == ExternalReference::DIRECT_GETTER_CALL) {
if (::v8::internal::FLAG_trace_sim || !stack_aligned) {
PrintF("Call to host function at %p args %08x %08x",
reinterpret_cast<void*>(external), arg0, arg1);
if (!stack_aligned) {
PrintF(" with unaligned stack %08x\n", get_register(sp));
}
PrintF("\n");
}
CHECK(stack_aligned);
SimulatorRuntimeDirectGetterCall target =
reinterpret_cast<SimulatorRuntimeDirectGetterCall>(external);
target(arg0, arg1);
} else if (
redirection->type() == ExternalReference::PROFILING_GETTER_CALL) {
if (::v8::internal::FLAG_trace_sim || !stack_aligned) {
PrintF("Call to host function at %p args %08x %08x %08x",
reinterpret_cast<void*>(external), arg0, arg1, arg2);
if (!stack_aligned) {
PrintF(" with unaligned stack %08x\n", get_register(sp));
}
PrintF("\n");
}
CHECK(stack_aligned);
SimulatorRuntimeProfilingGetterCall target =
reinterpret_cast<SimulatorRuntimeProfilingGetterCall>(
external);
target(arg0, arg1, Redirection::ReverseRedirection(arg2));
} else {
// builtin call.
DCHECK(redirection->type() == ExternalReference::BUILTIN_CALL ||
redirection->type() == ExternalReference::BUILTIN_CALL_PAIR);
SimulatorRuntimeCall target =
reinterpret_cast<SimulatorRuntimeCall>(external);
if (::v8::internal::FLAG_trace_sim || !stack_aligned) {
PrintF(
"Call to host function at %p "
"args %08x, %08x, %08x, %08x, %08x, %08x, %08x, %08x, %08x",
static_cast<void*>(FUNCTION_ADDR(target)), arg0, arg1, arg2, arg3,
arg4, arg5, arg6, arg7, arg8);
if (!stack_aligned) {
PrintF(" with unaligned stack %08x\n", get_register(sp));
}
PrintF("\n");
}
CHECK(stack_aligned);
int64_t result =
target(arg0, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8);
int32_t lo_res = static_cast<int32_t>(result);
int32_t hi_res = static_cast<int32_t>(result >> 32);
if (::v8::internal::FLAG_trace_sim) {
PrintF("Returned %08x\n", lo_res);
}
set_register(r0, lo_res);
set_register(r1, hi_res);
}
set_register(lr, saved_lr);
set_pc(get_register(lr));
break;
}
case kBreakpoint: {
ArmDebugger dbg(this);
dbg.Debug();
break;
}
// stop uses all codes greater than 1 << 23.
default: {
if (svc >= (1 << 23)) {
uint32_t code = svc & kStopCodeMask;
if (isWatchedStop(code)) {
IncreaseStopCounter(code);
}
// Stop if it is enabled, otherwise go on jumping over the stop
// and the message address.
if (isEnabledStop(code)) {
ArmDebugger dbg(this);
dbg.Stop(instr);
}
} else {
// This is not a valid svc code.
UNREACHABLE();
break;
}
}
}
}
float Simulator::canonicalizeNaN(float value) {
// Default NaN value, see "NaN handling" in "IEEE 754 standard implementation
// choices" of the ARM Reference Manual.
constexpr uint32_t kDefaultNaN = 0x7FC00000u;
if (FPSCR_default_NaN_mode_ && std::isnan(value)) {
value = bit_cast<float>(kDefaultNaN);
}
return value;
}
Float32 Simulator::canonicalizeNaN(Float32 value) {
// Default NaN value, see "NaN handling" in "IEEE 754 standard implementation
// choices" of the ARM Reference Manual.
constexpr Float32 kDefaultNaN = Float32::FromBits(0x7FC00000u);
return FPSCR_default_NaN_mode_ && value.is_nan() ? kDefaultNaN : value;
}
double Simulator::canonicalizeNaN(double value) {
// Default NaN value, see "NaN handling" in "IEEE 754 standard implementation
// choices" of the ARM Reference Manual.
constexpr uint64_t kDefaultNaN = uint64_t{0x7FF8000000000000};
if (FPSCR_default_NaN_mode_ && std::isnan(value)) {
value = bit_cast<double>(kDefaultNaN);
}
return value;
}
Float64 Simulator::canonicalizeNaN(Float64 value) {
// Default NaN value, see "NaN handling" in "IEEE 754 standard implementation
// choices" of the ARM Reference Manual.
constexpr Float64 kDefaultNaN =
Float64::FromBits(uint64_t{0x7FF8000000000000});
return FPSCR_default_NaN_mode_ && value.is_nan() ? kDefaultNaN : value;
}
// Stop helper functions.
bool Simulator::isStopInstruction(Instruction* instr) {
return (instr->Bits(27, 24) == 0xF) && (instr->SvcValue() >= kStopCode);
}
bool Simulator::isWatchedStop(uint32_t code) {
DCHECK_LE(code, kMaxStopCode);
return code < kNumOfWatchedStops;
}
bool Simulator::isEnabledStop(uint32_t code) {
DCHECK_LE(code, kMaxStopCode);
// Unwatched stops are always enabled.
return !isWatchedStop(code) ||
!(watched_stops_[code].count & kStopDisabledBit);
}
void Simulator::EnableStop(uint32_t code) {
DCHECK(isWatchedStop(code));
if (!isEnabledStop(code)) {
watched_stops_[code].count &= ~kStopDisabledBit;
}
}
void Simulator::DisableStop(uint32_t code) {
DCHECK(isWatchedStop(code));
if (isEnabledStop(code)) {
watched_stops_[code].count |= kStopDisabledBit;
}
}
void Simulator::IncreaseStopCounter(uint32_t code) {
DCHECK_LE(code, kMaxStopCode);
DCHECK(isWatchedStop(code));
if ((watched_stops_[code].count & ~(1 << 31)) == 0x7FFFFFFF) {
PrintF("Stop counter for code %i has overflowed.\n"
"Enabling this code and reseting the counter to 0.\n", code);
watched_stops_[code].count = 0;
EnableStop(code);
} else {
watched_stops_[code].count++;
}
}
// Print a stop status.
void Simulator::PrintStopInfo(uint32_t code) {
DCHECK_LE(code, kMaxStopCode);
if (!isWatchedStop(code)) {
PrintF("Stop not watched.");
} else {
const char* state = isEnabledStop(code) ? "Enabled" : "Disabled";
int32_t count = watched_stops_[code].count & ~kStopDisabledBit;
// Don't print the state of unused breakpoints.
if (count != 0) {
if (watched_stops_[code].desc) {
PrintF("stop %i - 0x%x: \t%s, \tcounter = %i, \t%s\n",
code, code, state, count, watched_stops_[code].desc);
} else {
PrintF("stop %i - 0x%x: \t%s, \tcounter = %i\n",
code, code, state, count);
}
}
}
}
// Handle execution based on instruction types.
// Instruction types 0 and 1 are both rolled into one function because they
// only differ in the handling of the shifter_operand.
void Simulator::DecodeType01(Instruction* instr) {
int type = instr->TypeValue();
if ((type == 0) && instr->IsSpecialType0()) {
// multiply instruction or extra loads and stores
if (instr->Bits(7, 4) == 9) {
if (instr->Bit(24) == 0) {
// Raw field decoding here. Multiply instructions have their Rd in
// funny places.
int rn = instr->RnValue();
int rm = instr->RmValue();
int rs = instr->RsValue();
int32_t rs_val = get_register(rs);
int32_t rm_val = get_register(rm);
if (instr->Bit(23) == 0) {
if (instr->Bit(21) == 0) {
// The MUL instruction description (A 4.1.33) refers to Rd as being
// the destination for the operation, but it confusingly uses the
// Rn field to encode it.
// Format(instr, "mul'cond's 'rn, 'rm, 'rs");
int rd = rn; // Remap the rn field to the Rd register.
int32_t alu_out = rm_val * rs_val;
set_register(rd, alu_out);
if (instr->HasS()) {
SetNZFlags(alu_out);
}
} else {
int rd = instr->RdValue();
int32_t acc_value = get_register(rd);
if (instr->Bit(22) == 0) {
// The MLA instruction description (A 4.1.28) refers to the order
// of registers as "Rd, Rm, Rs, Rn". But confusingly it uses the
// Rn field to encode the Rd register and the Rd field to encode
// the Rn register.
// Format(instr, "mla'cond's 'rn, 'rm, 'rs, 'rd");
int32_t mul_out = rm_val * rs_val;
int32_t result = acc_value + mul_out;
set_register(rn, result);
} else {
// Format(instr, "mls'cond's 'rn, 'rm, 'rs, 'rd");
int32_t mul_out = rm_val * rs_val;
int32_t result = acc_value - mul_out;
set_register(rn, result);
}
}
} else {
// The signed/long multiply instructions use the terms RdHi and RdLo
// when referring to the target registers. They are mapped to the Rn
// and Rd fields as follows:
// RdLo == Rd
// RdHi == Rn (This is confusingly stored in variable rd here
// because the mul instruction from above uses the
// Rn field to encode the Rd register. Good luck figuring
// this out without reading the ARM instruction manual
// at a very detailed level.)
// Format(instr, "'um'al'cond's 'rd, 'rn, 'rs, 'rm");
int rd_hi = rn; // Remap the rn field to the RdHi register.
int rd_lo = instr->RdValue();
int32_t hi_res = 0;
int32_t lo_res = 0;
if (instr->Bit(22) == 1) {
int64_t left_op = static_cast<int32_t>(rm_val);
int64_t right_op = static_cast<int32_t>(rs_val);
uint64_t result = left_op * right_op;
hi_res = static_cast<int32_t>(result >> 32);
lo_res = static_cast<int32_t>(result & 0xFFFFFFFF);
} else {
// unsigned multiply
uint64_t left_op = static_cast<uint32_t>(rm_val);
uint64_t right_op = static_cast<uint32_t>(rs_val);
uint64_t result = left_op * right_op;
hi_res = static_cast<int32_t>(result >> 32);
lo_res = static_cast<int32_t>(result & 0xFFFFFFFF);
}
set_register(rd_lo, lo_res);
set_register(rd_hi, hi_res);
if (instr->HasS()) {
UNIMPLEMENTED();
}
}
} else {
if (instr->Bits(24, 23) == 3) {
if (instr->Bit(20) == 1) {
// ldrex
int rt = instr->RtValue();
int rn = instr->RnValue();
int32_t addr = get_register(rn);
switch (instr->Bits(22, 21)) {
case 0: {
// Format(instr, "ldrex'cond 'rt, ['rn]");
int value = ReadExW(addr, instr);
set_register(rt, value);
break;
}
case 2: {
// Format(instr, "ldrexb'cond 'rt, ['rn]");
uint8_t value = ReadExBU(addr);
set_register(rt, value);
break;
}
case 3: {
// Format(instr, "ldrexh'cond 'rt, ['rn]");
uint16_t value = ReadExHU(addr, instr);
set_register(rt, value);
break;
}
default:
UNREACHABLE();
break;
}
} else {
// The instruction is documented as strex rd, rt, [rn], but the
// "rt" register is using the rm bits.
int rd = instr->RdValue();
int rt = instr->RmValue();
int rn = instr->RnValue();
DCHECK_NE(rd, rn);
DCHECK_NE(rd, rt);
int32_t addr = get_register(rn);
switch (instr->Bits(22, 21)) {
case 0: {
// Format(instr, "strex'cond 'rd, 'rm, ['rn]");
int value = get_register(rt);
int status = WriteExW(addr, value, instr);
set_register(rd, status);
break;
}
case 2: {
// Format(instr, "strexb'cond 'rd, 'rm, ['rn]");
uint8_t value = get_register(rt);
int status = WriteExB(addr, value);
set_register(rd, status);
break;
}
case 3: {
// Format(instr, "strexh'cond 'rd, 'rm, ['rn]");
uint16_t value = get_register(rt);
int status = WriteExH(addr, value, instr);
set_register(rd, status);
break;
}
default:
UNREACHABLE();
break;
}
}
} else {
UNIMPLEMENTED(); // Not used by V8.
}
}
} else {
// extra load/store instructions
int rd = instr->RdValue();
int rn = instr->RnValue();
int32_t rn_val = get_register(rn);
int32_t addr = 0;
if (instr->Bit(22) == 0) {
int rm = instr->RmValue();
int32_t rm_val = get_register(rm);
switch (instr->PUField()) {
case da_x: {
// Format(instr, "'memop'cond'sign'h 'rd, ['rn], -'rm");
DCHECK(!instr->HasW());
addr = rn_val;
rn_val -= rm_val;
set_register(rn, rn_val);
break;
}
case ia_x: {
// Format(instr, "'memop'cond'sign'h 'rd, ['rn], +'rm");
DCHECK(!instr->HasW());
addr = rn_val;
rn_val += rm_val;
set_register(rn, rn_val);
break;
}
case db_x: {
// Format(instr, "'memop'cond'sign'h 'rd, ['rn, -'rm]'w");
rn_val -= rm_val;
addr = rn_val;
if (instr->HasW()) {
set_register(rn, rn_val);
}
break;
}
case ib_x: {
// Format(instr, "'memop'cond'sign'h 'rd, ['rn, +'rm]'w");
rn_val += rm_val;
addr = rn_val;
if (instr->HasW()) {
set_register(rn, rn_val);
}
break;
}
default: {
// The PU field is a 2-bit field.
UNREACHABLE();
break;
}
}
} else {
int32_t imm_val = (instr->ImmedHValue() << 4) | instr->ImmedLValue();
switch (instr->PUField()) {
case da_x: {
// Format(instr, "'memop'cond'sign'h 'rd, ['rn], #-'off8");
DCHECK(!instr->HasW());
addr = rn_val;
rn_val -= imm_val;
set_register(rn, rn_val);
break;
}
case ia_x: {
// Format(instr, "'memop'cond'sign'h 'rd, ['rn], #+'off8");
DCHECK(!instr->HasW());
addr = rn_val;
rn_val += imm_val;
set_register(rn, rn_val);
break;
}
case db_x: {
// Format(instr, "'memop'cond'sign'h 'rd, ['rn, #-'off8]'w");
rn_val -= imm_val;
addr = rn_val;
if (instr->HasW()) {
set_register(rn, rn_val);
}
break;
}
case ib_x: {
// Format(instr, "'memop'cond'sign'h 'rd, ['rn, #+'off8]'w");
rn_val += imm_val;
addr = rn_val;
if (instr->HasW()) {
set_register(rn, rn_val);
}
break;
}
default: {
// The PU field is a 2-bit field.
UNREACHABLE();
break;
}
}
}
if (((instr->Bits(7, 4) & 0xD) == 0xD) && (instr->Bit(20) == 0)) {
DCHECK_EQ(rd % 2, 0);
if (instr->HasH()) {
// The strd instruction.
int32_t value1 = get_register(rd);
int32_t value2 = get_register(rd+1);
WriteDW(addr, value1, value2);
} else {
// The ldrd instruction.
int* rn_data = ReadDW(addr);
set_dw_register(rd, rn_data);
}
} else if (instr->HasH()) {
if (instr->HasSign()) {
if (instr->HasL()) {
int16_t val = ReadH(addr, instr);
set_register(rd, val);
} else {
int16_t val = get_register(rd);
WriteH(addr, val, instr);
}
} else {
if (instr->HasL()) {
uint16_t val = ReadHU(addr, instr);
set_register(rd, val);
} else {
uint16_t val = get_register(rd);
WriteH(addr, val, instr);
}
}
} else {
// signed byte loads
DCHECK(instr->HasSign());
DCHECK(instr->HasL());
int8_t val = ReadB(addr);
set_register(rd, val);
}
return;
}
} else if ((type == 0) && instr->IsMiscType0()) {
if ((instr->Bits(27, 23) == 2) && (instr->Bits(21, 20) == 2) &&
(instr->Bits(15, 4) == 0xF00)) {
// MSR
int rm = instr->RmValue();
DCHECK_NE(pc, rm); // UNPREDICTABLE
SRegisterFieldMask sreg_and_mask =
instr->BitField(22, 22) | instr->BitField(19, 16);
SetSpecialRegister(sreg_and_mask, get_register(rm));
} else if ((instr->Bits(27, 23) == 2) && (instr->Bits(21, 20) == 0) &&
(instr->Bits(11, 0) == 0)) {
// MRS
int rd = instr->RdValue();
DCHECK_NE(pc, rd); // UNPREDICTABLE
SRegister sreg = static_cast<SRegister>(instr->BitField(22, 22));
set_register(rd, GetFromSpecialRegister(sreg));
} else if (instr->Bits(22, 21) == 1) {
int rm = instr->RmValue();
switch (instr->BitField(7, 4)) {
case BX:
set_pc(get_register(rm));
break;
case BLX: {
uint32_t old_pc = get_pc();
set_pc(get_register(rm));
set_register(lr, old_pc + Instruction::kInstrSize);
break;
}
case BKPT: {
ArmDebugger dbg(this);
PrintF("Simulator hit BKPT.\n");
dbg.Debug();
break;
}
default:
UNIMPLEMENTED();
}
} else if (instr->Bits(22, 21) == 3) {
int rm = instr->RmValue();
int rd = instr->RdValue();
switch (instr->BitField(7, 4)) {
case CLZ: {
uint32_t bits = get_register(rm);
int leading_zeros = 0;
if (bits == 0) {
leading_zeros = 32;
} else {
while ((bits & 0x80000000u) == 0) {
bits <<= 1;
leading_zeros++;
}
}
set_register(rd, leading_zeros);
break;
}
default:
UNIMPLEMENTED();
}
} else {
PrintF("%08x\n", instr->InstructionBits());
UNIMPLEMENTED();
}
} else if ((type == 1) && instr->IsNopType1()) {
// NOP.
} else {
int rd = instr->RdValue();
int rn = instr->RnValue();
int32_t rn_val = get_register(rn);
int32_t shifter_operand = 0;
bool shifter_carry_out = 0;
if (type == 0) {
shifter_operand = GetShiftRm(instr, &shifter_carry_out);
} else {
DCHECK_EQ(instr->TypeValue(), 1);
shifter_operand = GetImm(instr, &shifter_carry_out);
}
int32_t alu_out;
switch (instr->OpcodeField()) {
case AND: {
// Format(instr, "and'cond's 'rd, 'rn, 'shift_rm");
// Format(instr, "and'cond's 'rd, 'rn, 'imm");
alu_out = rn_val & shifter_operand;
set_register(rd, alu_out);
if (instr->HasS()) {
SetNZFlags(alu_out);
SetCFlag(shifter_carry_out);
}
break;
}
case EOR: {
// Format(instr, "eor'cond's 'rd, 'rn, 'shift_rm");
// Format(instr, "eor'cond's 'rd, 'rn, 'imm");
alu_out = rn_val ^ shifter_operand;
set_register(rd, alu_out);
if (instr->HasS()) {
SetNZFlags(alu_out);
SetCFlag(shifter_carry_out);
}
break;
}
case SUB: {
// Format(instr, "sub'cond's 'rd, 'rn, 'shift_rm");
// Format(instr, "sub'cond's 'rd, 'rn, 'imm");
alu_out = rn_val - shifter_operand;
set_register(rd, alu_out);
if (instr->HasS()) {
SetNZFlags(alu_out);
SetCFlag(!BorrowFrom(rn_val, shifter_operand));
SetVFlag(OverflowFrom(alu_out, rn_val, shifter_operand, false));
}
break;
}
case RSB: {
// Format(instr, "rsb'cond's 'rd, 'rn, 'shift_rm");
// Format(instr, "rsb'cond's 'rd, 'rn, 'imm");
alu_out = shifter_operand - rn_val;
set_register(rd, alu_out);
if (instr->HasS()) {
SetNZFlags(alu_out);
SetCFlag(!BorrowFrom(shifter_operand, rn_val));
SetVFlag(OverflowFrom(alu_out, shifter_operand, rn_val, false));
}
break;
}
case ADD: {
// Format(instr, "add'cond's 'rd, 'rn, 'shift_rm");
// Format(instr, "add'cond's 'rd, 'rn, 'imm");
alu_out = rn_val + shifter_operand;
set_register(rd, alu_out);
if (instr->HasS()) {
SetNZFlags(alu_out);
SetCFlag(CarryFrom(rn_val, shifter_operand));
SetVFlag(OverflowFrom(alu_out, rn_val, shifter_operand, true));
}
break;
}
case ADC: {
// Format(instr, "adc'cond's 'rd, 'rn, 'shift_rm");
// Format(instr, "adc'cond's 'rd, 'rn, 'imm");
alu_out = rn_val + shifter_operand + GetCarry();
set_register(rd, alu_out);
if (instr->HasS()) {
SetNZFlags(alu_out);
SetCFlag(CarryFrom(rn_val, shifter_operand, GetCarry()));
SetVFlag(OverflowFrom(alu_out, rn_val, shifter_operand, true));
}
break;
}
case SBC: {
// Format(instr, "sbc'cond's 'rd, 'rn, 'shift_rm");
// Format(instr, "sbc'cond's 'rd, 'rn, 'imm");
alu_out = (rn_val - shifter_operand) - (GetCarry() ? 0 : 1);
set_register(rd, alu_out);
if (instr->HasS()) {
SetNZFlags(alu_out);
SetCFlag(!BorrowFrom(rn_val, shifter_operand, GetCarry()));
SetVFlag(OverflowFrom(alu_out, rn_val, shifter_operand, false));
}
break;
}
case RSC: {
Format(instr, "rsc'cond's 'rd, 'rn, 'shift_rm");
Format(instr, "rsc'cond's 'rd, 'rn, 'imm");
break;
}
case TST: {
if (instr->HasS()) {
// Format(instr, "tst'cond 'rn, 'shift_rm");
// Format(instr, "tst'cond 'rn, 'imm");
alu_out = rn_val & shifter_operand;
SetNZFlags(alu_out);
SetCFlag(shifter_carry_out);
} else {
// Format(instr, "movw'cond 'rd, 'imm").
alu_out = instr->ImmedMovwMovtValue();
set_register(rd, alu_out);
}
break;
}
case TEQ: {
if (instr->HasS()) {
// Format(instr, "teq'cond 'rn, 'shift_rm");
// Format(instr, "teq'cond 'rn, 'imm");
alu_out = rn_val ^ shifter_operand;
SetNZFlags(alu_out);
SetCFlag(shifter_carry_out);
} else {
// Other instructions matching this pattern are handled in the
// miscellaneous instructions part above.
UNREACHABLE();
}
break;
}
case CMP: {
if (instr->HasS()) {
// Format(instr, "cmp'cond 'rn, 'shift_rm");
// Format(instr, "cmp'cond 'rn, 'imm");
alu_out = rn_val - shifter_operand;
SetNZFlags(alu_out);
SetCFlag(!BorrowFrom(rn_val, shifter_operand));
SetVFlag(OverflowFrom(alu_out, rn_val, shifter_operand, false));
} else {
// Format(instr, "movt'cond 'rd, 'imm").
alu_out =
(get_register(rd) & 0xFFFF) | (instr->ImmedMovwMovtValue() << 16);
set_register(rd, alu_out);
}
break;
}
case CMN: {
if (instr->HasS()) {
// Format(instr, "cmn'cond 'rn, 'shift_rm");
// Format(instr, "cmn'cond 'rn, 'imm");
alu_out = rn_val + shifter_operand;
SetNZFlags(alu_out);
SetCFlag(CarryFrom(rn_val, shifter_operand));
SetVFlag(OverflowFrom(alu_out, rn_val, shifter_operand, true));
} else {
// Other instructions matching this pattern are handled in the
// miscellaneous instructions part above.
UNREACHABLE();
}
break;
}
case ORR: {
// Format(instr, "orr'cond's 'rd, 'rn, 'shift_rm");
// Format(instr, "orr'cond's 'rd, 'rn, 'imm");
alu_out = rn_val | shifter_operand;
set_register(rd, alu_out);
if (instr->HasS()) {
SetNZFlags(alu_out);
SetCFlag(shifter_carry_out);
}
break;
}
case MOV: {
// Format(instr, "mov'cond's 'rd, 'shift_rm");
// Format(instr, "mov'cond's 'rd, 'imm");
alu_out = shifter_operand;
set_register(rd, alu_out);
if (instr->HasS()) {
SetNZFlags(alu_out);
SetCFlag(shifter_carry_out);
}
break;
}
case BIC: {
// Format(instr, "bic'cond's 'rd, 'rn, 'shift_rm");
// Format(instr, "bic'cond's 'rd, 'rn, 'imm");
alu_out = rn_val & ~shifter_operand;
set_register(rd, alu_out);
if (instr->HasS()) {
SetNZFlags(alu_out);
SetCFlag(shifter_carry_out);
}
break;
}
case MVN: {
// Format(instr, "mvn'cond's 'rd, 'shift_rm");
// Format(instr, "mvn'cond's 'rd, 'imm");
alu_out = ~shifter_operand;
set_register(rd, alu_out);
if (instr->HasS()) {
SetNZFlags(alu_out);
SetCFlag(shifter_carry_out);
}
break;
}
default: {
UNREACHABLE();
break;
}
}
}
}
void Simulator::DecodeType2(Instruction* instr) {
int rd = instr->RdValue();
int rn = instr->RnValue();
int32_t rn_val = get_register(rn);
int32_t im_val = instr->Offset12Value();
int32_t addr = 0;
switch (instr->PUField()) {
case da_x: {
// Format(instr, "'memop'cond'b 'rd, ['rn], #-'off12");
DCHECK(!instr->HasW());
addr = rn_val;
rn_val -= im_val;
set_register(rn, rn_val);
break;
}
case ia_x: {
// Format(instr, "'memop'cond'b 'rd, ['rn], #+'off12");
DCHECK(!instr->HasW());
addr = rn_val;
rn_val += im_val;
set_register(rn, rn_val);
break;
}
case db_x: {
// Format(instr, "'memop'cond'b 'rd, ['rn, #-'off12]'w");
rn_val -= im_val;
addr = rn_val;
if (instr->HasW()) {
set_register(rn, rn_val);
}
break;
}
case ib_x: {
// Format(instr, "'memop'cond'b 'rd, ['rn, #+'off12]'w");
rn_val += im_val;
addr = rn_val;
if (instr->HasW()) {
set_register(rn, rn_val);
}
break;
}
default: {
UNREACHABLE();
break;
}
}
if (instr->HasB()) {
if (instr->HasL()) {
byte val = ReadBU(addr);
set_register(rd, val);
} else {
byte val = get_register(rd);
WriteB(addr, val);
}
} else {
if (instr->HasL()) {
set_register(rd, ReadW(addr, instr));
} else {
WriteW(addr, get_register(rd), instr);
}
}
}
void Simulator::DecodeType3(Instruction* instr) {
int rd = instr->RdValue();
int rn = instr->RnValue();
int32_t rn_val = get_register(rn);
bool shifter_carry_out = 0;
int32_t shifter_operand = GetShiftRm(instr, &shifter_carry_out);
int32_t addr = 0;
switch (instr->PUField()) {
case da_x: {
DCHECK(!instr->HasW());
Format(instr, "'memop'cond'b 'rd, ['rn], -'shift_rm");
UNIMPLEMENTED();
break;
}
case ia_x: {
if (instr->Bit(4) == 0) {
// Memop.
} else {
if (instr->Bit(5) == 0) {
switch (instr->Bits(22, 21)) {
case 0:
if (instr->Bit(20) == 0) {
if (instr->Bit(6) == 0) {
// Pkhbt.
uint32_t rn_val = get_register(rn);
uint32_t rm_val = get_register(instr->RmValue());
int32_t shift = instr->Bits(11, 7);
rm_val <<= shift;
set_register(rd, (rn_val & 0xFFFF) | (rm_val & 0xFFFF0000U));
} else {
// Pkhtb.
uint32_t rn_val = get_register(rn);
int32_t rm_val = get_register(instr->RmValue());
int32_t shift = instr->Bits(11, 7);
if (shift == 0) {
shift = 32;
}
rm_val >>= shift;
set_register(rd, (rn_val & 0xFFFF0000U) | (rm_val & 0xFFFF));
}
} else {
UNIMPLEMENTED();
}
break;
case 1:
UNIMPLEMENTED();
break;
case 2:
UNIMPLEMENTED();
break;
case 3: {
// Usat.
int32_t sat_pos = instr->Bits(20, 16);
int32_t sat_val = (1 << sat_pos) - 1;
int32_t shift = instr->Bits(11, 7);
int32_t shift_type = instr->Bit(6);
int32_t rm_val = get_register(instr->RmValue());
if (shift_type == 0) { // LSL
rm_val <<= shift;
} else { // ASR
rm_val >>= shift;
}
// If saturation occurs, the Q flag should be set in the CPSR.
// There is no Q flag yet, and no instruction (MRS) to read the
// CPSR directly.
if (rm_val > sat_val) {
rm_val = sat_val;
} else if (rm_val < 0) {
rm_val = 0;
}
set_register(rd, rm_val);
break;
}
}
} else {
switch (instr->Bits(22, 21)) {
case 0:
UNIMPLEMENTED();
break;
case 1:
if (instr->Bits(9, 6) == 1) {
if (instr->Bit(20) == 0) {
if (instr->Bits(19, 16) == 0xF) {
// Sxtb.
int32_t rm_val = get_register(instr->RmValue());
int32_t rotate = instr->Bits(11, 10);
switch (rotate) {
case 0:
break;
case 1:
rm_val = (rm_val >> 8) | (rm_val << 24);
break;
case 2:
rm_val = (rm_val >> 16) | (rm_val << 16);
break;
case 3:
rm_val = (rm_val >> 24) | (rm_val << 8);
break;
}