commit 61a8495e1e0485bd40f613004bf29f8a925ab37c
author Andrew Top <aabtop@google.com> Tue Apr 30 15:07:33 2019 -0700
committer Andrew Top <aabtop@google.com> Thu May 02 17:06:51 2019 -0700
tree 8b4860759d8854c2c58b6db4cf3ad2bf3f68aa5c
parent 193dc3d54bfe1fcc7a4d95650f8e9f2c8d9e7d1e

Import Cobalt 19.master.0.203780

Includes the following patches:
  https://cobalt-review.googlesource.com/c/cobalt/+/5210
    by errong.leng@samsung.com
  https://cobalt-review.googlesource.com/c/cobalt/+/5270
    by linus.wang@samsung.com

src/third_party/llvm-project/clang/test/CodeGenCXX/volatile.cpp

diff --git a/src/third_party/llvm-project/clang/test/CodeGenCXX/volatile.cpp b/src/third_party/llvm-project/clang/test/CodeGenCXX/volatile.cpp
new file mode 100644
index 0000000..9c0271b
--- /dev/null
+++ b/src/third_party/llvm-project/clang/test/CodeGenCXX/volatile.cpp
@@ -0,0 +1,35 @@
+// RUN: %clang_cc1 %s -triple=x86_64-apple-darwin10 -emit-llvm -std=c++98 -o - | FileCheck %s
+// RUN: %clang_cc1 %s -triple=x86_64-apple-darwin10 -emit-llvm -std=c++11 -o - | FileCheck -check-prefix=CHECK -check-prefix=CHECK11 %s
+
+// Check that IR gen doesn't try to do an lvalue-to-rvalue conversion
+// on a volatile reference result.  rdar://problem/8338198
+namespace test0 {
+  struct A {
+    A(const A& t);
+    A& operator=(const A& t);
+    volatile A& operator=(const volatile A& t) volatile;
+  };
+
+  volatile A *array;
+
+  // CHECK-LABEL: define void @_ZN5test04testENS_1AE(
+  void test(A t) {
+    // CHECK:      [[ARR:%.*]] = load [[A:%.*]]*, [[A:%.*]]** @_ZN5test05arrayE, align 8
+    // CHECK-NEXT: [[IDX:%.*]] = getelementptr inbounds [[A]], [[A]]* [[ARR]], i64 0
+    // CHECK-NEXT: [[TMP:%.*]] = call dereferenceable({{[0-9]+}}) [[A]]* @_ZNV5test01AaSERVKS0_([[A]]* [[IDX]], [[A]]* dereferenceable({{[0-9]+}}) [[T:%.*]])
+    // CHECK-NEXT: ret void
+    array[0] = t;
+  }
+}
+
+namespace test1 {
+  volatile int *x;
+
+  // CHECK-LABEL: define void @_ZN5test14testEv()
+  void test() {
+    // CHECK:      [[TMP:%.*]] = load i32*, i32** @_ZN5test11xE, align 8
+    // CHECK11-NEXT: {{%.*}} = load volatile i32, i32* [[TMP]], align 4
+    // CHECK-NEXT: ret void
+    *x;
+  }
+}