third_party/llvm-project/llvm/test/CodeGen/X86/GlobalISel/select-mul-vec.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s

--- |
  define <8 x i16> @test_mul_v8i16(<8 x i16> %arg1, <8 x i16> %arg2) #0 {
    %ret = mul <8 x i16> %arg1, %arg2
    ret <8 x i16> %ret
  }

  define <8 x i16> @test_mul_v8i16_avx(<8 x i16> %arg1, <8 x i16> %arg2) #1 {
    %ret = mul <8 x i16> %arg1, %arg2
    ret <8 x i16> %ret
  }

  define <8 x i16> @test_mul_v8i16_avx512bwvl(<8 x i16> %arg1, <8 x i16> %arg2) #2 {
    %ret = mul <8 x i16> %arg1, %arg2
    ret <8 x i16> %ret
  }

  define <4 x i32> @test_mul_v4i32(<4 x i32> %arg1, <4 x i32> %arg2) #3 {
    %ret = mul <4 x i32> %arg1, %arg2
    ret <4 x i32> %ret
  }

  define <4 x i32> @test_mul_v4i32_avx(<4 x i32> %arg1, <4 x i32> %arg2) #1 {
    %ret = mul <4 x i32> %arg1, %arg2
    ret <4 x i32> %ret
  }

  define <4 x i32> @test_mul_v4i32_avx512vl(<4 x i32> %arg1, <4 x i32> %arg2) #4 {
    %ret = mul <4 x i32> %arg1, %arg2
    ret <4 x i32> %ret
  }

  define <2 x i64> @test_mul_v2i64(<2 x i64> %arg1, <2 x i64> %arg2) #5 {
    %ret = mul <2 x i64> %arg1, %arg2
    ret <2 x i64> %ret
  }

  define <16 x i16> @test_mul_v16i16(<16 x i16> %arg1, <16 x i16> %arg2) #6 {
    %ret = mul <16 x i16> %arg1, %arg2
    ret <16 x i16> %ret
  }

  define <16 x i16> @test_mul_v16i16_avx512bwvl(<16 x i16> %arg1, <16 x i16> %arg2) #2 {
    %ret = mul <16 x i16> %arg1, %arg2
    ret <16 x i16> %ret
  }

  define <8 x i32> @test_mul_v8i32(<8 x i32> %arg1, <8 x i32> %arg2) #6 {
    %ret = mul <8 x i32> %arg1, %arg2
    ret <8 x i32> %ret
  }

  define <8 x i32> @test_mul_v8i32_avx512vl(<8 x i32> %arg1, <8 x i32> %arg2) #4 {
    %ret = mul <8 x i32> %arg1, %arg2
    ret <8 x i32> %ret
  }

  define <4 x i64> @test_mul_v4i64(<4 x i64> %arg1, <4 x i64> %arg2) #5 {
    %ret = mul <4 x i64> %arg1, %arg2
    ret <4 x i64> %ret
  }

  define <32 x i16> @test_mul_v32i16(<32 x i16> %arg1, <32 x i16> %arg2) #7 {
    %ret = mul <32 x i16> %arg1, %arg2
    ret <32 x i16> %ret
  }

  define <16 x i32> @test_mul_v16i32(<16 x i32> %arg1, <16 x i32> %arg2) #8 {
    %ret = mul <16 x i32> %arg1, %arg2
    ret <16 x i32> %ret
  }

  define <8 x i64> @test_mul_v8i64(<8 x i64> %arg1, <8 x i64> %arg2) #9 {
    %ret = mul <8 x i64> %arg1, %arg2
    ret <8 x i64> %ret
  }

  attributes #0 = { "target-features"="+sse2" }
  attributes #1 = { "target-features"="+avx" }
  attributes #2 = { "target-features"="+avx512vl,+avx512f,+avx512bw" }
  attributes #3 = { "target-features"="+sse4.1" }
  attributes #4 = { "target-features"="+avx512vl,+avx512f" }
  attributes #5 = { "target-features"="+avx2,+avx512vl,+avx512f,+avx512dq" }
  attributes #6 = { "target-features"="+avx2" }
  attributes #7 = { "target-features"="+avx512f,+avx512bw" }
  attributes #8 = { "target-features"="+avx512f" }
  attributes #9 = { "target-features"="+avx512f,+avx512dq" }

...
---
name:            test_mul_v8i16
alignment:       4
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; CHECK-LABEL: name: test_mul_v8i16
    ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
    ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
    ; CHECK: [[PMULLWrr:%[0-9]+]]:vr128 = PMULLWrr [[COPY]], [[COPY1]]
    ; CHECK: $xmm0 = COPY [[PMULLWrr]]
    ; CHECK: RET 0, implicit $xmm0
    %0(<8 x s16>) = COPY $xmm0
    %1(<8 x s16>) = COPY $xmm1
    %2(<8 x s16>) = G_MUL %0, %1
    $xmm0 = COPY %2(<8 x s16>)
    RET 0, implicit $xmm0

...
---
name:            test_mul_v8i16_avx
alignment:       4
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; CHECK-LABEL: name: test_mul_v8i16_avx
    ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
    ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
    ; CHECK: [[VPMULLWrr:%[0-9]+]]:vr128 = VPMULLWrr [[COPY]], [[COPY1]]
    ; CHECK: $xmm0 = COPY [[VPMULLWrr]]
    ; CHECK: RET 0, implicit $xmm0
    %0(<8 x s16>) = COPY $xmm0
    %1(<8 x s16>) = COPY $xmm1
    %2(<8 x s16>) = G_MUL %0, %1
    $xmm0 = COPY %2(<8 x s16>)
    RET 0, implicit $xmm0

...
---
name:            test_mul_v8i16_avx512bwvl
alignment:       4
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; CHECK-LABEL: name: test_mul_v8i16_avx512bwvl
    ; CHECK: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
    ; CHECK: [[COPY1:%[0-9]+]]:vr128x = COPY $xmm1
    ; CHECK: [[VPMULLWZ128rr:%[0-9]+]]:vr128x = VPMULLWZ128rr [[COPY]], [[COPY1]]
    ; CHECK: $xmm0 = COPY [[VPMULLWZ128rr]]
    ; CHECK: RET 0, implicit $xmm0
    %0(<8 x s16>) = COPY $xmm0
    %1(<8 x s16>) = COPY $xmm1
    %2(<8 x s16>) = G_MUL %0, %1
    $xmm0 = COPY %2(<8 x s16>)
    RET 0, implicit $xmm0

...
---
name:            test_mul_v4i32
alignment:       4
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; CHECK-LABEL: name: test_mul_v4i32
    ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
    ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
    ; CHECK: [[PMULLDrr:%[0-9]+]]:vr128 = PMULLDrr [[COPY]], [[COPY1]]
    ; CHECK: $xmm0 = COPY [[PMULLDrr]]
    ; CHECK: RET 0, implicit $xmm0
    %0(<4 x s32>) = COPY $xmm0
    %1(<4 x s32>) = COPY $xmm1
    %2(<4 x s32>) = G_MUL %0, %1
    $xmm0 = COPY %2(<4 x s32>)
    RET 0, implicit $xmm0

...
---
name:            test_mul_v4i32_avx
alignment:       4
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; CHECK-LABEL: name: test_mul_v4i32_avx
    ; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
    ; CHECK: [[COPY1:%[0-9]+]]:vr128 = COPY $xmm1
    ; CHECK: [[VPMULLDrr:%[0-9]+]]:vr128 = VPMULLDrr [[COPY]], [[COPY1]]
    ; CHECK: $xmm0 = COPY [[VPMULLDrr]]
    ; CHECK: RET 0, implicit $xmm0
    %0(<4 x s32>) = COPY $xmm0
    %1(<4 x s32>) = COPY $xmm1
    %2(<4 x s32>) = G_MUL %0, %1
    $xmm0 = COPY %2(<4 x s32>)
    RET 0, implicit $xmm0

...
---
name:            test_mul_v4i32_avx512vl
alignment:       4
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; CHECK-LABEL: name: test_mul_v4i32_avx512vl
    ; CHECK: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
    ; CHECK: [[COPY1:%[0-9]+]]:vr128x = COPY $xmm1
    ; CHECK: [[VPMULLDZ128rr:%[0-9]+]]:vr128x = VPMULLDZ128rr [[COPY]], [[COPY1]]
    ; CHECK: $xmm0 = COPY [[VPMULLDZ128rr]]
    ; CHECK: RET 0, implicit $xmm0
    %0(<4 x s32>) = COPY $xmm0
    %1(<4 x s32>) = COPY $xmm1
    %2(<4 x s32>) = G_MUL %0, %1
    $xmm0 = COPY %2(<4 x s32>)
    RET 0, implicit $xmm0

...
---
name:            test_mul_v2i64
alignment:       4
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $xmm0, $xmm1

    ; CHECK-LABEL: name: test_mul_v2i64
    ; CHECK: [[COPY:%[0-9]+]]:vr128x = COPY $xmm0
    ; CHECK: [[COPY1:%[0-9]+]]:vr128x = COPY $xmm1
    ; CHECK: [[VPMULLQZ128rr:%[0-9]+]]:vr128x = VPMULLQZ128rr [[COPY]], [[COPY1]]
    ; CHECK: $xmm0 = COPY [[VPMULLQZ128rr]]
    ; CHECK: RET 0, implicit $xmm0
    %0(<2 x s64>) = COPY $xmm0
    %1(<2 x s64>) = COPY $xmm1
    %2(<2 x s64>) = G_MUL %0, %1
    $xmm0 = COPY %2(<2 x s64>)
    RET 0, implicit $xmm0

...
---
name:            test_mul_v16i16
alignment:       4
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $ymm0, $ymm1

    ; CHECK-LABEL: name: test_mul_v16i16
    ; CHECK: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
    ; CHECK: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm1
    ; CHECK: [[VPMULLWYrr:%[0-9]+]]:vr256 = VPMULLWYrr [[COPY]], [[COPY1]]
    ; CHECK: $ymm0 = COPY [[VPMULLWYrr]]
    ; CHECK: RET 0, implicit $ymm0
    %0(<16 x s16>) = COPY $ymm0
    %1(<16 x s16>) = COPY $ymm1
    %2(<16 x s16>) = G_MUL %0, %1
    $ymm0 = COPY %2(<16 x s16>)
    RET 0, implicit $ymm0

...
---
name:            test_mul_v16i16_avx512bwvl
alignment:       4
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $ymm0, $ymm1

    ; CHECK-LABEL: name: test_mul_v16i16_avx512bwvl
    ; CHECK: [[COPY:%[0-9]+]]:vr256x = COPY $ymm0
    ; CHECK: [[COPY1:%[0-9]+]]:vr256x = COPY $ymm1
    ; CHECK: [[VPMULLWZ256rr:%[0-9]+]]:vr256x = VPMULLWZ256rr [[COPY]], [[COPY1]]
    ; CHECK: $ymm0 = COPY [[VPMULLWZ256rr]]
    ; CHECK: RET 0, implicit $ymm0
    %0(<16 x s16>) = COPY $ymm0
    %1(<16 x s16>) = COPY $ymm1
    %2(<16 x s16>) = G_MUL %0, %1
    $ymm0 = COPY %2(<16 x s16>)
    RET 0, implicit $ymm0

...
---
name:            test_mul_v8i32
alignment:       4
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $ymm0, $ymm1

    ; CHECK-LABEL: name: test_mul_v8i32
    ; CHECK: [[COPY:%[0-9]+]]:vr256 = COPY $ymm0
    ; CHECK: [[COPY1:%[0-9]+]]:vr256 = COPY $ymm1
    ; CHECK: [[VPMULLDYrr:%[0-9]+]]:vr256 = VPMULLDYrr [[COPY]], [[COPY1]]
    ; CHECK: $ymm0 = COPY [[VPMULLDYrr]]
    ; CHECK: RET 0, implicit $ymm0
    %0(<8 x s32>) = COPY $ymm0
    %1(<8 x s32>) = COPY $ymm1
    %2(<8 x s32>) = G_MUL %0, %1
    $ymm0 = COPY %2(<8 x s32>)
    RET 0, implicit $ymm0

...
---
name:            test_mul_v8i32_avx512vl
alignment:       4
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $ymm0, $ymm1

    ; CHECK-LABEL: name: test_mul_v8i32_avx512vl
    ; CHECK: [[COPY:%[0-9]+]]:vr256x = COPY $ymm0
    ; CHECK: [[COPY1:%[0-9]+]]:vr256x = COPY $ymm1
    ; CHECK: [[VPMULLDZ256rr:%[0-9]+]]:vr256x = VPMULLDZ256rr [[COPY]], [[COPY1]]
    ; CHECK: $ymm0 = COPY [[VPMULLDZ256rr]]
    ; CHECK: RET 0, implicit $ymm0
    %0(<8 x s32>) = COPY $ymm0
    %1(<8 x s32>) = COPY $ymm1
    %2(<8 x s32>) = G_MUL %0, %1
    $ymm0 = COPY %2(<8 x s32>)
    RET 0, implicit $ymm0

...
---
name:            test_mul_v4i64
alignment:       4
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $ymm0, $ymm1

    ; CHECK-LABEL: name: test_mul_v4i64
    ; CHECK: [[COPY:%[0-9]+]]:vr256x = COPY $ymm0
    ; CHECK: [[COPY1:%[0-9]+]]:vr256x = COPY $ymm1
    ; CHECK: [[VPMULLQZ256rr:%[0-9]+]]:vr256x = VPMULLQZ256rr [[COPY]], [[COPY1]]
    ; CHECK: $ymm0 = COPY [[VPMULLQZ256rr]]
    ; CHECK: RET 0, implicit $ymm0
    %0(<4 x s64>) = COPY $ymm0
    %1(<4 x s64>) = COPY $ymm1
    %2(<4 x s64>) = G_MUL %0, %1
    $ymm0 = COPY %2(<4 x s64>)
    RET 0, implicit $ymm0

...
---
name:            test_mul_v32i16
alignment:       4
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $zmm0, $zmm1

    ; CHECK-LABEL: name: test_mul_v32i16
    ; CHECK: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
    ; CHECK: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm1
    ; CHECK: [[VPMULLWZrr:%[0-9]+]]:vr512 = VPMULLWZrr [[COPY]], [[COPY1]]
    ; CHECK: $zmm0 = COPY [[VPMULLWZrr]]
    ; CHECK: RET 0, implicit $zmm0
    %0(<32 x s16>) = COPY $zmm0
    %1(<32 x s16>) = COPY $zmm1
    %2(<32 x s16>) = G_MUL %0, %1
    $zmm0 = COPY %2(<32 x s16>)
    RET 0, implicit $zmm0

...
---
name:            test_mul_v16i32
alignment:       4
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $zmm0, $zmm1

    ; CHECK-LABEL: name: test_mul_v16i32
    ; CHECK: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
    ; CHECK: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm1
    ; CHECK: [[VPMULLDZrr:%[0-9]+]]:vr512 = VPMULLDZrr [[COPY]], [[COPY1]]
    ; CHECK: $zmm0 = COPY [[VPMULLDZrr]]
    ; CHECK: RET 0, implicit $zmm0
    %0(<16 x s32>) = COPY $zmm0
    %1(<16 x s32>) = COPY $zmm1
    %2(<16 x s32>) = G_MUL %0, %1
    $zmm0 = COPY %2(<16 x s32>)
    RET 0, implicit $zmm0

...
---
name:            test_mul_v8i64
alignment:       4
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: vecr }
  - { id: 1, class: vecr }
  - { id: 2, class: vecr }
body:             |
  bb.1 (%ir-block.0):
    liveins: $zmm0, $zmm1

    ; CHECK-LABEL: name: test_mul_v8i64
    ; CHECK: [[COPY:%[0-9]+]]:vr512 = COPY $zmm0
    ; CHECK: [[COPY1:%[0-9]+]]:vr512 = COPY $zmm1
    ; CHECK: [[VPMULLQZrr:%[0-9]+]]:vr512 = VPMULLQZrr [[COPY]], [[COPY1]]
    ; CHECK: $zmm0 = COPY [[VPMULLQZrr]]
    ; CHECK: RET 0, implicit $zmm0
    %0(<8 x s64>) = COPY $zmm0
    %1(<8 x s64>) = COPY $zmm1
    %2(<8 x s64>) = G_MUL %0, %1
    $zmm0 = COPY %2(<8 x s64>)
    RET 0, implicit $zmm0

...