blob: c7abf81b60a11ab9cc25a2c9094dc0b67572ddad [file] [log] [blame]
name: drv_add_chanctx
ID: 1446
format:
field:unsigned short common_type; offset:0; size:2; signed:0;
field:unsigned char common_flags; offset:2; size:1; signed:0;
field:unsigned char common_preempt_count; offset:3; size:1; signed:0;
field:int common_pid; offset:4; size:4; signed:1;
field:char wiphy_name[32]; offset:8; size:32; signed:0;
field:u32 control_freq; offset:40; size:4; signed:0;
field:u32 freq_offset; offset:44; size:4; signed:0;
field:u32 chan_width; offset:48; size:4; signed:0;
field:u32 center_freq1; offset:52; size:4; signed:0;
field:u32 freq1_offset; offset:56; size:4; signed:0;
field:u32 center_freq2; offset:60; size:4; signed:0;
field:u32 min_control_freq; offset:64; size:4; signed:0;
field:u32 min_freq_offset; offset:68; size:4; signed:0;
field:u32 min_chan_width; offset:72; size:4; signed:0;
field:u32 min_center_freq1; offset:76; size:4; signed:0;
field:u32 min_freq1_offset; offset:80; size:4; signed:0;
field:u32 min_center_freq2; offset:84; size:4; signed:0;
field:u8 rx_chains_static; offset:88; size:1; signed:0;
field:u8 rx_chains_dynamic; offset:89; size:1; signed:0;
print fmt: "%s control:%d.%03d MHz width:%d center: %d.%03d/%d MHz min_control:%d.%03d MHz min_width:%d min_center: %d.%03d/%d MHz chains:%d/%d", REC->wiphy_name, REC->control_freq, REC->freq_offset, REC->chan_width, REC->center_freq1, REC->freq1_offset, REC->center_freq2, REC->min_control_freq, REC->min_freq_offset, REC->min_chan_width, REC->min_center_freq1, REC->min_freq1_offset, REC->min_center_freq2, REC->rx_chains_static, REC->rx_chains_dynamic