| # RUN: llvm-mc -triple=aarch64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s |
| # RUN: llvm-mc -triple=arm64 -mattr=+fp-armv8 -disassemble < %s 2>&1 | FileCheck %s |
| |
| # None of these instructions should be classified as unpredictable: |
| |
| # CHECK-NOT: potentially undefined instruction encoding |
| |
| # Stores from duplicated registers should be fine. |
| 0xe3 0x0f 0x80 0xa8 |
| # CHECK: stp x3, x3, [sp], #0 |
| |
| # d5 != x5 so "ldp d5, d6, [x5], #24" is fine. |
| 0xa5 0x98 0xc1 0x6c |
| # CHECK: ldp d5, d6, [x5], #24 |
| |
| # xzr != sp so "stp xzr, xzr, [sp], #8" is fine. |
| 0xff 0xff 0x80 0xa8 |
| # CHECK: stp xzr, xzr, [sp], #8 |
