| { |
| "context" : "{ : }", |
| "name" : "bb2 => bb18", |
| "statements" : [ |
| { |
| "accesses" : [ |
| { |
| "kind" : "read", |
| "relation" : "{ Stmt_bb3[i0] -> MemRef_B[i0] }" |
| }, |
| { |
| "kind" : "write", |
| "relation" : "{ Stmt_bb3[i0] -> MemRef_A[99 - i0] }" |
| } |
| ], |
| "domain" : "{ Stmt_bb3[i0] : i0 <= 99 and i0 >= 0 }", |
| "name" : "Stmt_bb3", |
| "schedule" : "{ Stmt_bb3[i0] -> [0, i0] }" |
| }, |
| { |
| "accesses" : [ |
| { |
| "kind" : "read", |
| "relation" : "{ Stmt_bb12[i0] -> MemRef_A[99 - i0] }" |
| }, |
| { |
| "kind" : "write", |
| "relation" : "{ Stmt_bb12[i0] -> MemRef_A[i0] }" |
| } |
| ], |
| "domain" : "{ Stmt_bb12[i0] : i0 <= 99 and i0 >= 0 }", |
| "name" : "Stmt_bb12", |
| "schedule" : "{ Stmt_bb12[i0] -> [1, i0] }" |
| } |
| ] |
| } |